verilog basics

1. The basic output port gate primitives must be written in front of the port list, basic gate primitives cases pseudonym optional (can not name);
2. n input primitive:
3. Identifiers case sensitive, uppercase and lowercase letters, numbers, underline (_) and $ Composition; * Variables only the first character is a letter or draw a line under;
4. Format indicator is not case sensitive (b, o, d, h);
5. In addition to the identifier, descriptive text may be free to use the space;
6. Not have any primitive or nested embodiment;
7. verilog vector expressed as vector [highest: lowest], expression can select some interval, if the selection interval unknowns x is returned outside the range of the original;
8. Common circuit function verification method are: Logic Simulation (through the excitation waveform applied to the circuit, the monitoring circuit logic simulation waveform determination) and the formal verification (to demonstrate the circuit function through complicated mathematical arguments, for large and complex circuit);
9. All types of nets are assigned at the beginning of the simulation is z, except trireg is x (the relevant switching level model);
10. Begin reg register type variable assigned to x;
11.  ? Representing the UDP input can be 0 or x;
12. UDP output timing must be declared as reg;