[STM32] DMA detailed

00. Table of Contents

01. Introduction to DMA

Direct memory access (DMA) is used to provide high-speed data transfer between peripherals and memory and between memory and memory. Data can be moved quickly through DMA without any CPU operation. The CPU resources saved in this way can be used for other operations.

The DMA controller is based on a complex bus matrix architecture, which combines a powerful dual AHB main bus architecture with an independent FIFO to optimize the system bandwidth.

The two DMA controllers have a total of 16 data streams (8 for each controller), and each DMA controller is used to manage the memory access requests of one or more peripherals. Each data stream can have up to 8 channels (or requests) in total. Each channel has an arbiter to handle the priority between DMA requests.

02. Main features of DMA

The main features of DMA are:
● Dual AHB main bus architecture, one for memory access and the other for peripheral access
● AHB slave programming interface that only supports 32-bit access
● Each DMA controller has 8 data streams, each The data stream has up to 8 channels (or request)
● Each data stream has a separate four-level 32-bit first-in-first-out memory buffer (FIFO), which can be used in FIFO mode or direct mode:
— FIFO mode: software available Select the threshold level to be 1/4, 1/2, or 3/4 of the FIFO size
— direct mode
Each DMA request immediately starts a transfer to the memory. When the DMA request is configured to transfer data in memory-to-peripheral mode in direct mode (FIFO disabled), the DMA will only preload one data from the memory to the internal FIFO to ensure that the DMA request is immediately transferred once the peripheral triggers the DMA request data.

● Through hardware, each data stream can be configured as:
— Supports conventional channels of peripheral to memory, memory to peripheral and memory to memory transfer
— It also supports double buffer channels on the memory side
● 8 data streams Each of them is connected to a dedicated hardware DMA channel (request)
● The priority between DMA data stream requests can be programmed by software (4 levels: very high, high, medium, and low), and it can be used under the same software priority Priority is determined by hardware (for example, request 0 has a higher priority than request 1)
● Each data stream also supports software-triggered memory-to-memory transfer (only for DMA2 controller)
● Channels for each data stream selection Request up to 8. This selection can be configured by software, allowing several peripherals to initiate DMA requests
. The number of data items to be transferred can be managed by the DMA controller or peripherals:
— DMA stream controller: the number of data items to be transferred is 1 to 65535, Available software programming
— Peripheral flow controller: The number of data items to be transferred is unknown and controlled by the source or target peripherals, which signal the end of the transfer through hardware
● Independent source and target transfer widths (bytes, half Word, word): When the data width of the source and destination are not equal, DMA automatically encapsulates/decapsulates the necessary transmission data to optimize the bandwidth. This feature is only available in FIFO mode.

● Incremental or non-incremental addressing for source and destination
● Supports incremental burst transmission of 4, 8 and 16 beats. The size of the burst increment can be configured by software and is usually equal to half of the size of the peripheral FIFO
● Each data stream supports circular buffer management
● 5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA FIFO error) , Direct mode error), perform a logical OR operation to generate a single interrupt request for each data stream

03. DMA block diagram

The DMA controller performs direct memory transfer: because it uses the AHB main bus, it can control the AHB bus matrix to initiate AHB transactions.
It can perform the following transactions:
● Peripheral to memory transfer
● Memory to peripheral transfer
● Memory to memory transfer

The DMA controller provides two AHB master ports: AHB memory port (used to connect to memory) and AHB peripheral port (used to connect to peripherals). However, to perform memory-to-memory transfers, the AHB peripheral port must also be able to access the memory.

The AHB slave port is used to program the DMA controller (it only supports 32-bit access).

System implementation of two DMA controllers

04. DMA transaction

A DMA transaction consists of a given number of data transfer sequences. The number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) can be programmed by software.
Each DMA transfer includes three operations:
● Addressing through the DMA_SxPAR or DMA_SxM0AR register to load data from the peripheral data register or memory unit.
● Through DMA_SxPAR or DMA_SxM0AR register addressing, store the loaded data to the peripheral data register or memory unit.
● The DMA_SxNDTR counter is decremented after the data storage is over. The counter contains the number of transactions that still need to be executed.

After the event is generated, the peripheral will send a request signal to the DMA controller. The DMA controller processes the request according to the channel priority. As long as the DMA controller accesses the peripheral, the DMA controller sends an acknowledgement signal to the peripheral. After the peripheral gets the confirmation signal from the DMA controller, it will immediately release its request. Once the peripheral invalidates the request, the DMA controller will release the acknowledge signal. If there are more requests, the peripheral can start the next transaction.

05. Channel selection

Each data stream is associated with a DMA request, which can be selected from 8 possible channel requests. This selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR register.

06. Arbiter

The arbiter provides 8 DMA data stream request management based on request priority for the two AHB master ports (memory and peripheral ports), and initiates the peripheral/memory access sequence.
Priority management is divided into two stages:
● Software: The priority of each data stream can be configured in the DMA_SxCR register. Divided into four levels:
— Very high priority
— High priority
— Medium priority
— Low priority
● Hardware: If two requests have the same software priority, the data stream with the lower number has priority over the data stream with the higher number . For example, data stream 2 has a higher priority than data stream 4.

07. DMA data stream

All 8 DMA controller data streams can provide a unidirectional transmission link between source and destination.
After each data stream is configured, you can execute:
● General type transactions: transfer from memory to peripheral, peripheral to memory, or memory to memory.
● Double-buffer type transaction: double-buffer transfer using two memory pointers of the memory (when the DMA is reading/writing from/to the buffer, the application can write/read to/from other buffers operating).
The amount of data to be transferred (up to 65535) can be programmed and is related to the source width of the peripheral (requesting DMA transfer) connected to the peripheral AHB port. After each transaction is completed, the register containing the total amount of data items to be transferred will decrement.

08. DMA interrupt

For each DMA data stream, an interrupt can be generated when the following events occur:
● Half-transfer is reached
● Transmission is complete
● Transmission error
● FIFO error (overflow, underflow or FIFO level error)
● Direct mode error

09. DMA register

9.1 DMA low interrupt status register (DMA_LISR)

DMA low interrupt status register
offset address: 0x00
reset value: 0x0000 0000

9.2 DMA High Interrupt Status Register (DMA_HISR)

DMA high interrupt status register
offset address: 0x04
reset value: 0x0000 0000

9.3 DMA low interrupt flag clear register (DMA_LIFCR)

DMA low interrupt flag clear register
offset address: 0x08
reset value: 0x0000 0000

9.4 DMA high interrupt flag clear register (DMA_HIFCR)

DMA high interrupt flag clear register
offset address: 0x0C
reset value: 0x0000 0000

9.5 DMA data stream x configuration register (DMA_SxCR) (x = 0…7)

DMA stream x configuration register
This register is used to configure related data streams.
Offset address: 0x10 + 0x18 × data stream number
Reset value: 0x0000 0000

9.6 DMA data stream x number of data items register (DMA_SxNDTR) (x = 0…7)

DMA stream x number of data register
offset address: 0x14 + 0x18 × data stream number
Reset value: 0x0000 0000

9.7 DMA data stream x peripheral address register (DMA_SxPAR) (x = 0…7)

DMA stream x peripheral address register
offset address: 0x18 + 0x18 × data stream number
Reset value: 0x0000 0000

9.8 DMA data stream x memory 0 address register (DMA_SxM0AR) (x = 0…7)

DMA stream x memory 0 address register
offset address: 0x1C + 0x18 × data stream number
Reset value: 0x0000 0000

9.9 DMA data stream x memory 1 address register (DMA_SxM1AR) (x = 0…7)

DMA stream x memory 1 address register
offset address: 0x20 + 0x18 × data stream number
Reset value: 0x0000 0000

9.10 DMA data stream x FIFO control register (DMA_SxFCR) (x = 0…7)

DMA stream x FIFO control register
offset address: 0x24 + 0x24 × data stream number
Reset value: 0x0000 0021

10. Appendix

10.1 [STM32] STM32 series tutorial summary

Website: [STM32] STM32 series tutorial summary

11. Statement

STM32F4xx Chinese Reference Manual.pdf