DMA controller 8237A

1 Introduction to DMA system

DMA (direct memory access) is a way to directly transfer data between peripherals and memory or memory and memory. When DMA access is performed, the CPU gives up bus control and does not use input and output instructions for data access , And a dedicated hardware DMAC (Direct Memory Access Control) control circuit is used to reduce the intermediate links, thereby increasing the transmission rate.

1.1 Basic principles of DMA

DMA directly realizes the data transfer between I/O and memory.
①When the I/O interface is ready and hope to perform DMA operation, it is like DMAC sends out DMA request signal DRQ (DMA Request)
②DMAC converts this request signal into a bus request signal to the CPU (Hold Request)
③The CPU current bus execution cycle ends , Corresponding to the DMAC operation, the response signal HLDA (Hold Acknowledgment) is issued. At this time, the DMAC takes over the control of the bus. The
DMAC addresses the memory and sends out the corresponding control signals (DACK, /RD, /WR) to make the memory Directly exchange data with the I/O interface ⑤When transferring
a byte of data, the DMAC automatically modifies the memory address and the transfer byte counter, and detects whether the transfer is over.
⑥The DMA transfer is over, the DMAC sends an end signal (EOP) to the CPU, and Release the bus, allowing the CPU to regain control of the bus and resume normal operation

2 DMA controller 8237A

2.1 Overview of 8237A

1. 8237A is a programmable DMA controller;
2. Each 8237A has 4 independent DMA channels with different priorities;
3. Each DMA channel has 4 working modes;
4. The maximum length of one transmission can reach 64KB;
5. Multiple 8237A chips can be cascaded to expand the number of channels.

2.2 Internal structure of 8237A

2.3 8237A pin diagram

1. Control signals:
   (1) CLK: clock (control chip internal operation and data transmission)
   (2) ADSTB: address strobe
   (3)/cs: chip select
   (4) READY: ready
   (5) AEN: address allowed
   (6) )/MEMR: Memory read
   (7) RESET: Reset
   (8)/MEMW: Memory write
   (9) /IOR: I/O read
   (10)/EOP: End of process
   (11) / IOW: I/O write
2. Request and response signal
   (1) DREQ ₀ ~ DREQ ₃ : DMA channel request
   (2) HRQ: Bus request
   (3) HLDA: Bus response
   (4) DACK ₀ ~ DACK ₃ : DMA channel response
3. Data and address signals
   (1) A ₀～A ₇：Address line
   (2) DB ₀～DB ₇：Data line

2.4 8237A transmission timing

(1) Si state: idle cycle, one or several DREQ requests are detected on the falling edge of Si, and a DMA request is issued to the CPU on the next rising edge of Si, and HRQ is valid;
(2) S0 state: waiting for the CPU to request the bus The rising edge of S0 is sampled until the HLDA signal is valid, and the next cycle enters the S1 state;
(3) S1 state: the address enable signal AEN is valid, and the high 8-bit address of the storage unit is _output through DB0 _{DB7, and the address strobe signal ADSTB is issued, The falling edge latches the high 8-bit address, the low 8-bit address/} output _{by the address line A0} A7, and is maintained during the entire DMA transfer;
(4) S2 state: 8237A outputs DMA response signal DACK to the peripheral, read and write signals successively Valid;
(5) S3 state and S4 state for data transmission;
(6) In block transmission mode: the next byte is transmitted after S4, the upper 8 bits of the address remain unchanged, and the lower 8 bits change, without the need for S1 to directly enter S2 until A TC event occurred.
(7) If the data transmission cannot be completed before S4, READY can be made low and Sw is inserted between S3 and S4 to widen the DMA transmission cycle.

2.5 8237A working method

2.5.1 Single byte transmission mode

(1) Transmission process: After the 8237A obtains the bus control right, it transmits a byte, the byte number register is reduced by 1, the address register is increased or decreased by 1, HRQ becomes invalid, the bus is released, HRQ is effective again soon, and HLDA is received After the valid signal, transfer the next byte, and repeat the above process until the number of bytes is reduced from 0 to FFFFH, a TC event occurs, and the DMA transfer ends.
(2) Features: Low efficiency, but it can ensure that the CPU has the opportunity to regain control of the bus between two DMA transfers.

2.5.2 Block transfer method

(1) Transmission process: After being started by DREQ, data is continuously transmitted until a TC event occurs or a valid /EOP signal is input from the outside.
(2) Features: One data block can be transferred at one request, which is highly efficient; but the CPU cannot control the bus for a long time during the entire DMA transfer.

2.5.3 Request transmission method

Continuously transmit data and stop when one of the following three conditions occurs.
(1) The byte count register is reduced from 0 to FFFFH, and a TC event occurs;
(2) A valid signal is sent from the outside;
(3) The DREQ signal input from the outside becomes invalid.
When the third situation occurs, the transfer can continue when the peripheral is ready for data.
Features: DMA operation can be controlled by the peripheral to transfer the process.

2.5.4 Cascade transmission mode

Several pieces of 8237A form a master-slave DMA system

2.6 8237A transmission type

1. DMA read: data is transferred from the memory to the peripheral
2. DMA write: the data input by the peripheral is written into the memory
3. DMA check: No operation, the timing signal and address signal are the same as when reading and writing, but the reading and writing control line is invalid, it is often used for check.
4. Memory-to-memory transfer: Channel 0 is the source, channel 1 is the destination, and the software is started. Each byte transfer requires 8 clock cycles. The first 4 clock cycles are used to read data from the source area into the temporary register of the 8237A, and the last 4 Write the data in the temporary register into the destination area in one clock cycle until the TC event occurs or the /EOP signal is sent.

2.7 8237A Register Bank

1. Current address register: used to save the current address value transferred by DMA.
2. Current byte count register: It stores the number of bytes to be transferred.
3. Base address register: save the initial value of the current address.
4. Base byte number register: save the initial value of the current byte number.
5. Mode register: save the corresponding channel mode control word.
6. Command register: set 8237A operation mode
   
7. Request register: DREQ request can be issued by software during data block transfer, and channel 0 must be activated by software request when transferring from memory to memory.
   
8. Mask register: used to mask the DREQ request sent by the peripheral.
   
   (2) Main shield word format
   
9. Status register: Read the working status of 8237A from CPU.
10. Temporary register: save data in memory to memory transfer mode

2.8 8237A software commands

There are 10 kinds of internal registers in 237A, and the operation of them sometimes requires 3 software commands. 8237A "software command" features:
(1) No need to write control word through the data bus;
(2) Directly realized by address and control signal decoding.

1. Clear high/low flip-flop software command
   High/low flip-flop controls the reading and writing of 16-bit registers:
   flip-flop is 0, operating low byte;
   flip-flop is 1, operating high byte;
   16-bit register performs one operation, flip-flop
   The state changes automatically;
   A3A2A1A0=1100, the high/low trigger is cleared.
2. The main clear command
   has the same function as the hardware RESET signal,
   A3A2A1A0=1101
3. Clear mask register command
   to clear all 4 mask bits (allow DMA request)
   A3A2A1A0 = 1110