DMA

(Direct memory access)

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DMA (Direct Memory Access) is an important feature of all modern computers . It allows hardware devices of different speeds to communicate without relying on the massive interrupt load of the CPU. Otherwise, the CPU needs to copy the data of each segment from the source to the scratchpad , and then write them back to the new place again. During this time, the CPU cannot be used for other tasks.

Chinese name

Direct memory access

Foreign name

Direct Memory Access

Abbreviation

DMA

Features

Different speed hardware devices to communicate

Source

Embedded bottom driver

principle

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DMA transfers copy data from one address space to another address space. When the CPU initiates this transfer action, the transfer action itself is implemented and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Operations like this did not delay the processor's work, but could be rescheduled to handle other tasks. DMA transmission is very important for high-performance embedded system algorithms and networks.

DMA

When implementing DMA transfer, the DMA controller directly controls the bus. Therefore, there is a problem of bus control transfer. That is, before the DMA transfer, the CPU must transfer the bus control to the DMA controller, and after the DMA transfer is completed, the DMA controller should immediately return the bus control to the CPU. A complete DMA transmission process must go through the 4 steps of DMA request, DMA response, DMA transmission, and DMA end.

request

The CPU initializes the DMA controller and issues an operation command to the I/O interface , and the I/O interface makes a DMA request.

response

The DMA controller discriminates the priority and shielding of the DMA request, and makes a bus request to the bus arbiter logic. When the CPU finishes executing the current bus cycle, it can release bus control. At this time, the bus arbitration logic outputs a bus response, indicating that the DMA has responded, and the DMA controller informs the I/O interface to start DMA transfer.

transmission

After the DMA controller obtains the bus control right, the CPU immediately suspends or only performs internal operations, and the DMA controller outputs read and write commands to directly control the RAM and I/O interface for DMA transfer.

Under the control of the DMA controller, data transfer is carried out directly between the memory and the external device, without the participation of the central processing unit during the transfer process. The starting position and data length of the data to be transmitted must be provided at the beginning.

End

When the specified batch data transfer is completed, the DMA controller releases bus control and sends an end signal to the I/O interface. When the I/O interface receives the end signal, on the one hand, it stops the work of the I/O device, and on the other hand, it sends an interrupt request to the CPU to free the CPU from the state of not intervening, and perform a period to check the correctness of this DMA transfer operation Code. Finally, continue to execute the original program with the results and status of this operation.

It can be seen that the DMA transmission method does not require the CPU to directly control the transmission, and there is no interruption processing method to retain the scene and restore the scene. The hardware opens up a direct data transmission path for the RAM and I/O devices, making the CPU more efficient. improve.

Delivery method

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The emergence of DMA technology allows peripheral devices to directly access the memory through the DMA controller. At the same time, the CPU can continue to execute programs. So how do DMA controller and CPU use memory in time sharing? The following three methods are usually used: (1) Stop CPU accessing memory; (2) Cycle embezzlement; (3) DMA and CPU alternately access memory.

Stop CPU access to memory

When the peripheral device requests to transmit a batch of data, the DMA controller sends a stop signal to the CPU, requesting the CPU to give up the right to use the address bus, data bus and related control buses. After the DMA controller obtains the bus control right, it starts data transfer. After a batch of data is transferred, the DMA controller informs the CPU that the memory can be used, and returns the bus control to the CPU. Figure (a) is a time chart of this transmission method. Obviously, in this DMA transfer process, the CPU is basically in a non-working state or holding state.

Advantages: Simple control, it is suitable for group transmission of equipment with high data transmission rate.

Disadvantages: When the DMA controller accesses the memory, the performance of the memory is not fully utilized, and a considerable part of the memory work cycle is idle. This is because the interval between the transmission of two data by peripheral devices is generally greater than the memory storage cycle, even for high-speed I/O devices. For example, it takes about 32us to read an 8-bit binary number from a floppy disk, while the storage cycle of semiconductor memory is less than 0.5us, so many idle storage cycles cannot be used by the CPU.

Cycle embezzlement

When the I/O device does not have a DMA request, the CPU accesses the memory as required by the program; once the I/O device has a DMA request, one or several memory cycles are appropriated by the I/O device.

The time chart of this transmission method is as follows (b):

Two situations may be encountered when the I/O device requires DMA transfer:

(1) At this time, the CPU does not need to visit internally, such as the CPU is executing multiplication instructions. Due to the long execution time of the multiplication instruction, there is no conflict between the I/O access and the CPU access at this time, that is, the I/O device embezzling one or two memory cycles has no effect on the CPU execution program.

(2) When the I/O device requests the internal visit, the CPU also requires the internal visit, which creates an internal visit conflict. In this case, the I/O device visits the internal priority because there is a time requirement for the I/O internal visit. I/O data must be accessed before the next access request comes. Obviously, in this case, the I/O device embezzles one or two memory cycles, which means that the CPU delays the execution of instructions, or more specifically, inserts a DMA request during the execution of the instruction in the CPU, embezzling one or two memory cycles. Two memory cycles. Compared with the DMA method of stopping CPU access, the method of cycle embezzlement not only realizes the I/O transfer, but also better exerts the efficiency of the memory and CPU, which is a widely used method. However, I/O devices have the process of applying for bus control rights, establishing line control rights, and returning bus control rights for every cycle embezzlement. Therefore, it takes one cycle for the memory to transmit a word, but it generally takes a cycle for the DMA controller. 2-5 memory cycles (depending on the delay of the logic circuit). Therefore, the cycle embezzlement method is suitable for I/O device read and write cycles greater than the memory storage cycle.

DMA and CPU alternately access memory

If the working cycle of the CPU is much longer than the memory access cycle, the alternate access method can make DMA transfer and the CPU play the highest efficiency at the same time.

The time chart of this transmission method is as follows:

This figure is a detailed time chart of alternate visits between DMA and CPU. Assuming that the CPU work cycle is 1.2us and the memory access cycle is less than 0.6us, then a CPU cycle can be divided into two sub-cycles, C1 and C2, where C1 is exclusively for the DMA controller and C2 is exclusively for the CPU.

This method does not require the application, establishment and return process of the bus use right. The bus use right is through the C1 and C2 time-sharing system. The CPU and the DMA controller each have their own internal access address register, data register, and read/write signal control registers. In the C1 cycle, if the DMA controller has an internal access request, it can send signals such as address and data to the bus. In the C2 cycle, if the CPU has an internal access request, it also transmits signals such as address and data. In fact, for the bus, which is C1, C2 to control a multiplexer converter , this shift control of the bus require little time, so the DMA transfer is very high in terms of efficiency.

This kind of transfer method is also called "transparent DMA" method. The reason is that this kind of DMA transfer is like transparent glass to the CPU without any feeling or influence. Working in a transparent DMA mode, the CPU neither stops the operation of the main program nor enters the waiting state, which is a highly efficient working mode. Of course, the corresponding hardware logic is more complicated.

Entry Atlas

DMA (Baidu Encyclopedia)

DMA