[Original] describes the SPI protocol, and the IP core based Verilog

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| I_clk |. 1 | input | module clock signals |
| I_rst_n |. 1 | input | module reset signal, active low |
| I_en |. 1 | input | module enable signal, or enable |
| O_spi_clk |. 1 | Output | the SPI clock signal the SCLK |
| O_spi_cs_n |. 1 | output | the SPI chip select enable signal CSn |
| IO_spi_data |. 1 | bidirectional port | the SPI data signal (three-wire) |
| I_tx_flag |. 1 | input | the SPI transmission signal, high effective |
| I_tx_data | on configuration | input | transmission data of the SPI |
| I_rx_flag |. 1 | input | reception signal SPI high effective |
| O_rx_data | on configuration | outputs | received data the SPI |
| O_rx_dval |. 1 | output | SPI receive data valid signal data, high effective |

The following code is given direct download link [ Click here ] Well, where the 3-wire mode 0 has been validated, for all other cases has not been verified, subsequent verification will update file.