Table of contents
2. Common command parameters of VCS
I. Introduction
Take Makefile to start VCS as an example to explain how to use command parameters. VCS compiled files will introduce too many parameters. Imagine that if we need to type too many parameters in the terminal to run VCS every time, the efficiency is obviously very low. Therefore, it is necessary to store parameters in scripting language to simplify operation instructions, so Makefile comes in handy.
We usually write the parameters into the Makefile, and then simplify the command into make run_vcs through the script to complete the compilation, connection and operation of VCS in one step. This is called one-step method (the first parameter is vcs).
2. Common command parameters of VCS
command parameters | meaning | Replenish |
vlog | Analyze verilog files (if analyzing VHDL files, similar instructions are vhdlan), and compile commonly used | used in the three-step method (see below) |
vcs | Compile the file using vcs | Use in one-step or two-step method (see below) |
-sverilog | The compiled file contains sv syntax, and this item must be added when compiling the sv file | vcs -sverilog tb.sv compile tb.sv file |
-full64 | Compile in 64-bit mode and create a 64-bit executable for emulation | If it is a 64-bit operating system, you must add |
-l compile.log | Write the compiled content to the compile.log file | |
+v2k(-v2k) | Using the Verilog 1364-2001 standard | widely used standard |
-f | Compile overrides .v files and files that include paths | vcs -f ram.lst Compile the lst file of ram, which may contain paths such as /home/host/rtl/ram.v |
-timescale=1ns/1ps | Define the time unit of the simulation as 1ns, and the precision is 1ps | Specify timetables for files that do not contain the timescale compiler directive, and specify timetables before files containing timetables |
+plusarg_save | Enable the parameter passing function, and specific values can be passed in during simulation | |
-ntb_opts | Add some options when compiling | -ntb_opts uvm1.2 means loading uvm1.2 library file |
+incdir+<directory> | Specifies the directory containing the files specified using the `include compiler directive. Multiple directories can be specified, separating each path name with a + character; | |
-debug_all | Start all debugging functions, -debug part of debugging, -debug_access+<option> (debug optional function added after VCS2014 version) | |
-nc | Do not print synopsys copyright information | Adding or not adding does not affect the simulation |
-R | Start the simulation immediately after compiling | one-step method |
-yes_res | enable time resolution |
Note: When incdir files, only the files under the folder can be included, not the contents of the lower-level folders (if you want to include the contents of the lower-level folders, you need to write +incdir+uvm/{test, test/basic_test}, which includes the files in the test file under uvm, and also includes the files in basic_test under test under uvm)
2.1. One-step method
When using VCS to compile and check design/verification files, it can be realized with only some simple VCS instructions. The following operations are suitable for use when no simulation is involved, and only to check whether the currently written file has errors.
Order | result |
vcs +v2k -full64 file1.v file2.v | Compile Verilog files |
vcs +v2k -full64 -sverilog file1.v file2.v file3.sv file4.sv | Compile files that can contain SV syntax |
vcs +v2k -full64 -f file1.lst | Compile the lst file, which contains the file information of the path |
If you need to start the simulation after compiling (prerequisite: have a verification environment), and there are many files, and you need to add more control parameters, you need to use Makefile. The following is a one-step Makefile writing example
One-step Makefile writing example:
Combine compilation and simulation operations through the -R option to achieve a one-step method
2.2. Two-step method
We sometimes split the compilation and simulation. After the compilation is completed and the simv file is generated, then the simulation is executed to execute the simv file, which is called a two-step method.
Two-step Makefile writing example:
Compared with the one-step method, split it into two steps, while not using the -R parameter
Supplement: The -gui parameter is optional, it controls to open the graphical interface, you can open verdi or dve, dve is native to vcs, and verdi is widely used
2.3. Three-step method
Compared with the two-step method, the three-step method splits compilation into analysis and refinement. It is generally used when compiling multiple file types (such as verilog and VHDL). In fact, this is divided into steps according to the actual operation process of VCS. The operation process of VCS is to temporarily store the compiled files, and then refine them into executable files. simv, and finally complete the file compilation and simulation by executing the .simv file.
First implement the analysis command in the Makefile (the first parameter is vlogan or vhdlan, compile verilog and VHDL files respectively, where an is the abbreviation of analysis), then implement the refinement command (the first parameter is vcs), and finally implement the simulation command.
Three-step Makefile compilation example
3. Common errors
cannot find vcs compiler
If you don’t compile with Makefile, you will often use less compilation parameters. For example, if you lack -full64, you will report cannot find vcs compiler. In addition, if you compile the sv file, if you do not add -sverilog, you will report a syntax error (syntax error)
4. References
About the detailed process of VCS simulation:
VCS simulation process_A6B's blog-CSDN blog_vcs vlogan
Makefile detailed writing example:
[Digital IC Quick Start] Makefile script understanding_Thomas-w's blog-CSDN blog_makefile script
Usage of =, :=, += in Makefile
The meaning of =, =, ?= and += in Makefile_keep_forward's blog-CSDN blog_in makefile:=
debug option
When compiling with Synopsys VCS, enable the debug option - XtremeDV Blog - CSDN Blog