What is makefile
Makefile : Makefile is an automatic compilation tool for source files under Linux. The source files in a project are not counted. They are placed in several directories according to type, function, and module. Makefile defines a series of rules to specify which files Which files need to be compiled first, which files need to be compiled later, which files need to be recompiled, or even more complex functional operations. Makefile is like a Shell script, which can also execute operating system commands
make : make is a command tool that interprets the instructions in the makefile. The advantage of makefile is "automatic compilation". Once written, only one make command is needed, and the entire project is fully compiled automatically. Improve the efficiency of software development
makefile
When the make command is executed, a makefile file is needed to tell the make command how to compile and link the program. The file name must be "Makefile" or "makefile" or "GNUmakefile". If other names are used, you need to use Make command -f or -file parameter to specify, such as "make -f MakeLinux"
Most make supports the default file names of "makefile" and "Makefile", so it is best to use them as the file name
Makefile writing rules :
target:prerequisites
command
target is the object file to be generated (Object File), it can also be an executable file or a label
prerequisites is to generate the necessary preconditions target file
Commnd is the command (Shell command) required to generate target by prerequisites
Note: Use Tab to indent before commnd
This is a file dependency, that is, one or more target files of target depend on the files in prerequisites, and the generation rules are defined in the command
In the makefile, the order in which the rules are written is very important. There should be a final goal in the makefile, and all other goals are linked by this goal. Let make know your final goal. The goal in the first rule in the makefile will be established as the final goal . If there are many goals in the first rule, then the first goal will become the final goal. What make accomplishes is this goal
For example, the following picture: (main is the final goal)
Use variables
Variables are data types used by computer systems to store variable values. We can directly extract the corresponding variable value through the variable name. Is to replace some settings or a string of reserved data with a set of words or symbols, etc.
How to use variables:
- Definition: Use = to define
- Use: $(variable name)
For example: there are 5 .o files in the above example, which can be defined as follows
file=my_add.o my_sub.o my_mux.o\
my_div.o main.o
Backslash \ is the meaning of newline character. To use these 5 .o files in the future, just use $(file)
For other introductions of variables and environment variables, please refer to my previous blog: Linux: Introduction to Shell, BASH and Shell Script
Document search
In some large projects, there are a large number of source files. Our usual practice is to classify these many source files and store them in different directories. So, when make needs to find the dependencies of files, you can add a path in front of the file, but the best way is to tell make a path and let make find it automatically
The special variable VPATH in makefile implements this function. If this variable is not specified, make will only look for dependent files and target files in the current directory. If this variable is defined, then make will look for files in the specified directory if the current directory cannot be found
VPATH usage rules :
VPATH=path1:path2
Two paths are specified above, separated by a colon:
You can also use the keyword vpath of make to set the file search path. Vapth is all lowercase, which is different from VPATH, which is a keyword and VPATH is a variable.
Vpath usage rules :
vpath <pattern> <directories> #为符合模式<pattern>的文件指定搜索路径<directories>
vpath<pattern> #清除符合模式<pattern>的文件的搜索目录
vpath #清除所有已被设置好了的文件搜索目录
Example: vpath %.c path1 indicates that the search directory of the specified .c file is path1,% indicates that zero or several characters are matched
Obscure rules
GNU's make is very powerful. It can automatically derive the commands behind files and file dependencies, so we don’t need to write similar commands after each .o file, because our make will automatically recognize it and use it by itself. Derive the command
As long as make sees a .o file, it will automatically add the .c file to the dependency. If make finds a whatever.o, then whatever.c will be a dependency file of whatever.o. And gcc -c whatever.c will also be deduced, this is the obscure rules of make
According to the obscure rules and variables, the first example can be simplified, as shown in the figure below:
Reference other makefiles
Use the include keyword in the maikefile file to include other makefiles, and the included files will be placed in the include location of the current file as they are
include syntax:
include file1 file2 file3
file can be the file format of the current operating system Shell, can include paths and wildcards, or use variables
False target
The target in the makefile writing rules can also be a pseudo target, such as a clear command
clean:
rm *.o
After executing the rm *.o command, a clean file will not be generated. Clean is just a label, which is vividly called a pseudo target
You can use .PHONY to explicitly indicate that a target is a pseudo target
.PHONY:clean
clean:
rm *.o
Note : Every makefile should write a command to clear the object files (.o and execution files) in order to recompile and keep the files clean. The unwritten rule is-"clean is always placed at the end of the file ", make will regard the first target appearing in the makefile as the default target. Others will not be executed unless it is needed to generate the default target . Therefore, the clean will not be executed during make. To execute the clean command, manually use the make clean command to clear the *.o file
Make work execution process
The following steps are executed when GNU make works:
- Read in all makefiles
- Read in other makefiles included
- Variables in the initialization file
- Derive obscure rules and analyze all rules
- Create relationship dependency chains for all target files
- According to the dependencies, decide which targets to regenerate
- Execute build command