Some knowledge of makefile

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foreword

  A series of rules are defined in the makefile to specify which files need to be compiled first, which files need to be compiled later, which files need to be recompiled, and even more complex functional operations, because makefile is like a shell script, which also The command of the operating system can be executed. The advantage of makefile is - "automatic compilation", once it is written, only one make command is needed, and the entire project is completely automatically compiled , which greatly improves the efficiency of software development.

  make is a command tool, a command tool that interprets the instructions in the makefile. Generally speaking, most IDEs have this command, such as: nmake of Visual C++, make of GNU under Linux. It can be seen that makefiles have become a compilation method in engineering.

  The makefile will use the gcc compiler to compile the source code, and finally generate an executable file or a library file.

  The name of the makefile file: makefile or Makefile

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提示：以下是本篇文章正文内容，下面案例可供参考

First, the basic rules of makefile

A makefile consists of a set of rules, the rules are as follows:

Goal: Dependency
(tab) command

Three elements of makefile basic rules:

• target : The target file to generate.

• Dependency : Which files the object file is generated from.

• Command : Generate the target from the dependency file by executing this command.

The following is a specific example to explain:

main.cFor example, there are , fun1.c, fun2.c, and , in the current directory sum.c. According to this basic rule, write a simple makefilefile to generate an executable file main.

method one:

• 1. Check it out, all the files are there
  
• 2. Create a makefilefile
  
• 3. makefileEnter the following two lines in the file:

1) The first line
mian: (represents the target, we name the target mian)
mian.c fun1.c fun2.c sum.c (these are the dependent files of the target)

2) The second line of
tab has a space (this space area can only use the tab key, and tab once)
the gcc compile command on the street behind

• 3. The make command generates the target file

• 4. Execution
  
  method 2:

main:main.o fun1.o fun2.o sum.o
        gcc -o main main.o fun1.o fun2.o sum.o

mian.o:mian.c
        gcc -c mian.c -I./
fun1.o:fun1.c
        gcc -c fun1.c 
fun2.o:fun2.c
        gcc -c fun2.c 
sum.o:sum.c
        gcc -c sum.c

Second, the working principle of makefile

  Basic principle: To generate a target, check that all dependent files in the rule exist:

• ① If some dependent files do not exist , search down the rules to see if there is a rule to generate the dependent file;
  ② If there is a rule to generate the dependent file , execute the command in the rule to generate the dependent file;
  ③ If there is no rule If it is used to generate the dependency file , an error will be reported.

• If all dependencies exist , check whether the target in the rule needs to be updated. You must first check all its dependencies. If any of the dependencies are updated, the target must be updated
  . time > dependent time, do not update
  if target time < dependent time, update

• Summary:
  Analyze the relationship between each target and its dependencies.
  Execute commands from the bottom up
  according to the dependencies. Determine whether to update according to the time of the dependent file and the time of the target file.
  If the target does not depend on any conditions, execute the corresponding command to show the update (such as : pseudo target)

3. Variables in makefile

  Using variables in makefileC language is somewhat similar to the macro definition in C language. Using this variable is equivalent to content substitution. Using variables can make it makefileeasy to maintain and easy to modify.

There are three types of variables in makefiles:

• Ordinary variable

• own variables

• automatic variable

3.1 Ordinary variables

① Directly use variable definition =
② Use variable value with $(variable name)

Such as: the following is the definition and use of
foo = abcvariables // define variables and assign values
bar = $(foo)​​// use variables, $(variable name)

  Two variables are defined: foo、bar, where barthe value is fooa reference to the variable's value.

  In addition to using user-defined variables, makefilesome variables (variable names are capitalized) are also provided for users to use directly, and we can assign them directly:

CC = gcc #arm-linux-gcc
CPPFLAGS : C预处理的选项 -I
CFLAGS: C编译器的选项 -Wall -g -c
LDFLAGS : 链接器选项 -L -l

3.2 Automatic variables

$@: Represents the target in the
$<rule: Represents the first condition in the
$^rule: Represents all the conditions in the rule, forming a list, separated by spaces, and eliminating duplicates if there are duplicates in this list.

Note: Automatic variables can only be used in the command of a rule.

3.3 Pattern Rules

  At least '%' should be included in the target definition of the rule, '%' means one or more, and '%' can also be used in the dependency condition. The value of '%' in the dependency condition depends on its target:

For example: main.o:main.c fun1.o: fun1.c fun2.o:fun2.c, the simple point is: xxx.o:xxx.c

Version 3 of the makefile:

target=main
object=main.o fun1.o fun2.o sum.o
CC=gcc
#makefile提供
CPPFLAGS=-I./  
#C预处理的选项 -I

$(target):$(object)
        $(CC) -o $@ $^ 
#$@是规则中的目标  $<表示规则中的第一个条件  $^表示规则中>的所有条件

%.o:%.c
        $(CC) -o $@ -c $< $(CPPFLAGS)

Four, makefile function

makefileThere are many functions in , and here are the two most commonly used ones.

1.wildcard – find files of the specified type in the specified directory
src=$(wildcard *.c)//find all files with the suffix .c in the current directory and assign them to src
2.patsubst – match and replace
obj=$(patsubst %.c,%.o, $(src))//replace all files with the suffix .c in the src variable into.o

All functions in makefiles have return values.
In the current directory, there is main.c fun1.c fun2.c sum.c is
src=$(wildcard *.c)equivalent to src=main.c fun1.c fun2.c sum.c is
obj=$(patsubst %.c,%.o, $(src))equivalent to obj=main.o fun1.o fun2.o sum.o

4th version of the makefile::

src=$(wildcard ./*.c)
object=$(patsubst %.c, %.o, $(src))
target=main
CC=gcc
CPPFLAGS=-I./

$(target):$(object)
        $(CC) -o $@ $^

%.o:%.c
        $(CC) -o $@ -c $< $(CPPFLAGS)

Disadvantage: Each recompilation requires manual cleanup of intermediate .o files and final object files

Five, makefile clean-up operation

Purpose: Clear the intermediate .o files and final object files generated by compilation

make clean If there is a clean file with the same name in the current directory, the command corresponding to clean will not be executed. Solution:

• Pseudo target declaration:
  .PHONY:clean
  After declaring a target as a pseudo target, the makefile will not check whether the target exists or whether the target needs to be updated

• cleanSpecial symbols in commands:
  " -" This command has an error, and make will continue to execute subsequent commands. Such as: “ -rm main.o”
  rm -f: Forced execution, for example, if the file to be deleted does not exist, it -fwill not report an error
  . “ @” does not display the command itself, only the result. Such as: " @echo clean done"

• Other
  – makedefaults to execute the first appearing target, by make destspecifying the target to be executed
  – make -f: -fexecute a makefilefile name, use makethe execution specifiedmakefile: make -f mainmak

Version 5 of the makefile:

src=$(wildcard ./*.c)
object=$(patsubst %.c, %.o, $(src))
target=main
CC=gcc
CPPFLAGS=-I./

$(target):$(object)
        $(CC) -o $@ $^

%.o:%.c
        $(CC) -o $@ -c $< $(CPPFLAGS)

.PHONY:clean
clean:
        -rm -f $(target) $(object)

Summarize

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