PGA hardware design is different from the DSP and ARM systems, more flexible and free. Good circuit design as long as special pins, universal I / O connection can define their own. Therefore, the circuit design of the FPGA there will be some special skill can refer to.
1. FPGA pin compatibility Design
When the option FPGA chip package to try to select a good compatibility. So, the hardware circuit design, it is necessary to consider how many chips compatibility issues. For example, EP2C8Q208C8 and EP2C5Q208 these two types of FPGA. Chip which only a dozen I / O pins are different definitions. On EP2C5Q208 chip, these I / O is a general purpose I / O pins, and in the EP2C8Q208C8 chips, they are power and ground signals. In order to ensure that the two chips can work on the same circuit board, we have come to the corresponding pin is connected to power and ground planes in accordance with the requirements EP2C5Q208. Because general-purpose I / O may be connected to power or ground signal, but the signal can not be power or as general purpose I / O. In the same package, compatible with a plurality of FPGA design models, according to the general principles of a small number of chip general purpose I / O circuit design.
2. The pin functions assigned to circuit layout
FPGA general purpose I / O function definition can be specified as needed. In the circuit design process, if the pin can be defined in accordance with the principle of adjusting the layout of the PCB corresponding to FIG FPGA, the wiring work can be more smoothly later. For example, as shown on the left side in FIG. 2-10 SDRAM chip in the FPGA. When the FPGA pin assignments, should be associated with SDRAM signal pin is arranged on the left side of the FPGA. This ensures that the signal wiring SDRAM shortest distance, for optimum signal integrity.
3. FPGA preset test points
FPGA currently provide an I / O number more and more, to meet the design requirements in addition to the I / O, there are some remaining I / O is not defined. These I / O can be used as test points reserved. For example, when the operation sequence SDRAM and the FPGA test connected state, the associated pin SDRAM directly oscilloscope measurement can be difficult. SDRAM and a higher operating frequency, direct measurement introduces additional impedance, affecting the normal operation of SDRAM. If there are reserved FPGA test points, the test signal may be specified from the FPGA to these test points reserved. This will not only test the waveforms of these signals, it will not affect the work of SDRAM. If the circuit was found during testing fly line needs to solve the problem, then these test points can also be reserved as a transition point of the fly line.
This switched small flat electronic technology community: https://www.xiaopingtou.cn/article-104214.html embedded, networking, hardware PCB, electronic technology all in a small flat