1 CISC RISC 与
(1) CPU model: arithmetic and controller
A complex instruction set and reduced instruction set (depending on N)
N = 111 (8051) Complex Instruction Set
N = 34 (ARM) RISC
SWAP (1) MOV (3) (a function on behalf of three MOV instruction SWAP) 2/8 law (twenty percent of frequently used instructions)
(2) Language: compiled and interpretative
Compiled (local language): directly generate machine code
Interpreted: such as: Java, compile once run everywhere (JVM itself is a process, to allocate memory space, converting the byte code into machine code, the user program included in this process)
(3) RISC (reduced instruction set) architecture features
Fixed-length instruction format, is determined to facilitate PC
Single-cycle instruction, to facilitate pipelining
Using a large number of registers, the memory access by LS structure
Which uses a CISC processors have the opposite characteristics, but more powerful processor CISC X86 architecture has
2, development tools
(1) tool Introduction:
And cross compiler tool chain and provider of
post and naming compiler tool chain is: Arch -vendor -os - (the GNU) EABI
ARM / mips providers target 0s Embedded Application Binary Interface
such as:
arm-none-eabi-gcc compiler for ARM trees machine (ubt, kernel), not compile the application associated with the os, by GNU
arm-none-linux-gnueabi-gcc ARM-based program rack village 2inux system, including uboot, kernel, Linux applications by
armccARM official compiler tool chain, functionality and arm-hone-eabi similar
(2) ARM official development tools: ADS, RVDS, KEIL (MDK-arm), DS-5 Development KEIL (MDK): The compiler uses is armcc, development environment: uVision IDE, only supports ARM7 / 9 and the entire department Cortex- M, does not support the cortex-A series.
DS5: compiler uses is armcc or arm-none-eabi-gcc, development environments: Eclipse, support the full range of core AM.
(3) KEIL MDK-ARM C51 uVision IDE
KEIL: company name, was acquired ARM
MDK-ARM (Microcontroller Development Kit) : specifically for the ARM core development kit
C51: Development Kit for 8051
uVision IDE: for project management, source code editing
3, MDK-ARM using (software installation / engineering establishment)
(1) Project --- New uVision Project
(2) Select the CPU (Sumsung-s3c2440), the boot code is not added
(3) File-New saved named startup.s
(4) Add .s file:
(5) Write the code (note that adding TAB):
Point: equivalent while (1)
(6) defined ROM
(7) remove the check, click Edit (remove warning):
Remove the line:
(8) compilation:
4, addressing
(1) Instruction Format
<Mnemonic> {<execution condition>} {S} <dest>, <action register number 1> {, <operand 2>)
note:
<Entry in the> number are required; (MOV, LDR, etc.)
Item numbers in {} are optional;
S: not affect the value of the CPSR, impact writing the CPSR
CMP without adding "s" can be changed corresponding flag
example: SUBS the PC, the LR, #. 4
MOV R0, # 0X00
the LDR R0, [Rl]
All instructions are 32bit (ARM instruction), load / store architecture ( access to the memory can only be achieved using load and store instructions)
(2) condition codes and machine code
using the instruction condition code can be achieved by an efficient editing operation, efficient code.
For example: if (a> b) a ++; CMP R0, R1
++ B the else; ADDHI R0, R0, #. 1
ADDLs Rl, Rl, #. 1 (the LS: less)
Note: CPSR flag bits inside (not referred to) corresponding to the mnemonic code condition (mind)
Common condition code: EQ NE HI LS
Encoding: MOV R0, # 0 × 00 <1110 0011 1010 0000000> 0xE3 A0 0000