---- Reprinted from: http://www.cnblogs.com/loleng/archive/2011/06/14/2080447.html
Often we see a different expression ARM7, ARM9, ARM11, and armv6k and so on. And in the GCC compiler, often use -march, -mcpu and so on. What they were expressing the meaning of it? Sam it is not very clear, but there are about a vague concept. Today it is a closer look.
ARM (Advanced RISC Machines) is the microprocessor industry, a well-known enterprises. We designed a large number of high-performance, low-cost, low power consumption RISC processors, related technologies and software. In 1985, the first prototype ARM was born in Cambridge, England. ARM's chip design features only, not production. ARM has licensed its technology to many of the world's leading semiconductor, software and OEM manufacturers, it is a unique ARM-related technologies and services obtained by each vendor. With this partnership, ARM RISC soon become the global standard in many of the founders.
ARM company defines six main instruction set architecture versions. V1-V6. (Therefore, the above-mentioned means ARMv6 instruction set version number). Namely: ARM architecture
ＡＲＭｖ１：
This version of the prototype is ARM1, not for commercial products.
ＡＲＭｖ２：
Version of V1 has been extended to include support for 32-bit result of the multiplication instruction and coprocessor instructions.
ＡＲＭｖ３：
ARM's first microprocessor core ARM6 version 3, as IP core, independent processor having on-chip cache, and write buffer of the MMU integrated CPU.
ARMv4:
Currently the most widely used instruction set version of the ARM.
ARM7TDMI, ARM720T, ARM9TDMI, ARM940T, ARM920T, Intel 's StrongARM, etc. are based on ARMv4T version.
ARMv5:
ARM9E-S, ARM966E-S, ARM1020E, ARM 1022E and XScale are the ARMv5TE.
ARM9EJ-S, ARM926EJ-S, ARM7EJ-S, ARM1026EJ-S is based on the ARMv5EJ.
ARM10 also be used.
Where the suffix meaning is as follows:
E: Enhanced DSP instruction set. It includes all 16-bit multiply operations and algorithms.
J: support the new Java.
ARMv6:
Using ARMv6 core ARM11 family processors.
ARM1136J (F) -S main features are based ARMv6 SIMD, Thumb, Jazelle, DBX, (VFP), MMU.
ARM1156T2 (F) -S ARMv6T2 The main features are based on SIMD, Thumb-2, (VFP), MPU.
The ARM1176JZ (F) -S based ARMv6KZ increase in (F) -S ARM1136EJ based on the MMU, TrustZone.
ARM11 MPCore ARMv6K based on (F) -S ARM1136EJ on the basis of core 1-4 may include SMP, MMU.
ARMv7-A：
ARM processor cores:
ARM has developed a number of ARM processor cores, the latest bit ARM11.
ARM7 microprocessor family
of low-power 32-bit RISC processor von Neumann architecture. Very low power consumption for portable products.
ICE-RT with embedded logic developed to facilitate debugging.
3-stage pipeline structure. Possible to provide a three-stage pipeline structure 0.9MIPS
high code density, compatible with the 16-bit Thumb instruction set.
Broad support for operating systems, including Windows CE, Linux, Palm OS and so on.
Instruction and ARM9 series, ARM9E series and ARM10E series compatible, user-friendly product upgrading.
Clocked at up to 130MIPS.
A variety of multimedia applications and embedded industrial control, Internet equipment, network and modem equipment, mobile phones: The main application areas.
ARM7TDMI microprocessor
four types:
ARM7TDMI, ARM7TDMI-S, the ARM720T, the ARM7EJ.
ARM7TMDI is currently the most widely used 32-bit embedded RISC processor, is a low-end ARM processor core.
Note: "ARM core" not chip, ARM core with other components, such as RAM, ROM, a combination of on-chip peripherals together to constitute a real chip.
ARM9 family of microprocessors
ARM9 family microprocessor to provide the best performance in terms of high performance and low power consumption.
Level 5 integer pipeline,
Harvard architecture.
32-bit 16-bit ARM instruction set and the Thumb instruction set.
Full performance of MMU, supports Windows CE, Linux, Palm OS and other mainstream embedded operating system.
Support Data Cache and Instruction Cache, with higher command and data processing capabilities.
Main applications: wireless equipment, instrumentation, safety systems, set-top boxes, high-end printers, digital cameras and digital video cameras.
3 types: ARM920T, ARM922T and ARM940T.
ARM9E microprocessor series
single processor core microcontrollers, DSP, Java application system solutions.
Support DSP instruction set.
5-stage integer pipeline, the higher efficiency of instruction execution.
32-bit 16-bit ARM instruction set and the Thumb instruction set.
VFP9 support floating-point processing coprocessor.
Full performance of MMU, supports Windows CE, Linux, Palm OS and other mainstream embedded operating system.
The MPU supports real-time operating system.
Support Data Cache and Instruction Cache,
clocked at up to 300MIPS.
The main application: The next generation of wireless field devices, digital consumer, the image forming apparatus, industrial control, storage devices and network equipment.
Three types: ARM926EJ-S, ARM946E-S and ARM966E-S.
ARM10E microprocessor series
compared with the same ARM9, at the same clock frequency, performance increased by nearly 50 percent, extremely low power consumption.
Support DSP instruction set.
6-stage integer pipeline, the higher efficiency of instruction execution.
32-bit 16-bit ARM instruction set and the Thumb instruction set.
VFP10 support floating-point processing coprocessor.
Full performance of MMU, supports Windows CE, Linux, Palm OS and other mainstream embedded operating system.
Support Data Cache and Instruction Cache.
Clocked at up to 400MIPS.
Embedded concurrent read / write operation member.
The main application: The next generation of wireless field devices, digital consumer, the image forming apparatus, industrial control, telecommunications and information systems.
3 types: ARM1020E, ARM1022E and ARM1026EJ-S.
SecurCore microprocessor family
designed for the security needs and designed to provide a complete 32-bit RISC technology security solutions.
Flexible protection unit to ensure the safety of the operating system and application data.
Soft core technology, it is scanned to prevent outside detection.
Users can integrate their security features and other coprocessors.
Main applications: for applications requiring higher security products and applications, such as e-commerce, e-government, e-banking, network and authentication systems.
4 types: SecurCore SC100, SecurCore SC110, SecurCore SC200 and SecurCore SC210.
Xscale processor
-based solutions ARMv5TE architecture, is a full-performance, cost-effective, low-power processors.
Support Thumb instructions and 16-bit DSP instruction set.
Has been used in digital mobile phones, personal digital assistants and network products and other occasions.
Intel Xscale processor is currently a major promotion of ARM microprocessors
ARM11: ARMv6,8 stage pipeline instruction set, 1.25DMIPS / MHz
Cortex-A8: Instruction Set ARMv7-A, 13-stage integer pipeline, superscalar dual emission, 2.0DMIPS / MHz, Neon standard, does not support multi-core
Scorpion: Instruction Set ARMv7-A, the high-pass access to basic instruction set of the authorization A8 on the design. 13 integer pipeline, superscalar dual emission, partially out of order execution, 2.1DMIPS / MHz, Neon standard, multi-core
Cortex-A9: Instruction Set ARMv7-A, 8-stage integer pipeline, dual emission superscalar, out of order, 2.5DMIPS / MHz, optional Neon / VFPv3, multi-core
Cortex-A5: instruction set ARMv7-A, 8-stage integer pipeline, 1.57DMIPS / MHz, optional Neon / VFPv3, multi-core
Cortex-A15: Instruction Set ARMv7-A, superscalar, out of order, optional Neon / VFPv4, multi-core
When using ARM toolchain, there -march -mcpu and so on.
-mcpu=
-mtune =
They specify the target processor (target ARM processor).
可选的参数为：arm2', `arm250', `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', `arm700i', `arm710', `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7tdmi', `arm7tdmi-s', `arm8', `strongarm', `strongarm110', `strongarm1100', `arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t', `arm922t', `arm946e-s', `arm966e-s', `arm968e-s', `arm926ej-s', `arm940t', `arm9tdmi', `arm10tdmi', `arm1020t', `arm1026ej-s', `arm10e', `arm1020e', `arm1022e', `arm1136j-s', `arm1136jf-s', `mpcore', `mpcorenovfp', `arm1176jz-s', `arm1176jzf-s', `xscale', `iwmmxt', `ep9312'，Cortex-A8， Cortex-A9
-march=
target ARM architecture. The target processor architecture.
`armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5', `armv5t', `armv5te', `armv6', `armv6j', `iwmmxt', `ep9312'. armv7-a等。
Reprinted: http://blog.sina.com.cn/s/blog_602f87700100kaa3.html
| Architecture | Processor Family |
|---|---|
| ARMv1 | ARM1 |
| ARMv2 | ARM2 , ARM3 |
| ARMv3 | ARM6, ARM7 |
| ARMv4 | StrongARM, ARM7TDMI, ARM9TDMI |
| ARMv5 | ARM7EJ, ARM9E, ARM10E, XScale |
| ARMv6 | ARM11, ARM Cortex-M |
| ARMv7 | ARM Cortex-A, ARM Cortex-M, ARM Cortex-R |
| ARMv8 |
Thumb
Newer ARM processors there is a 16-bit instruction mode, called Thumb, perhaps with each condition type operation instruction are consumed four circumstances related. Thumb mode, smaller opcode has less functionality. For example, only branches can be conditional expressions, and many opcode can not access all of the CPU registers. However, shorter opcode provide better overall code density (Note: the code means the space occupied in memory), even though some operations require more instructions. Especially in ports or the memory bus width is limited to the case of 32 or less, a shorter Thumb opcode more efficient use of the limited memory bandwidth, thus providing a better than 32-bit code performance. A typical embedded hardware having only a small 32-bit datapath and other addressing range narrower address 16 bits (e.g., Game Boy on Advance ). In this case, the program is generally compiled into viable Thumb code, and optimizing the use of some (non Thumb) related to the CPU instruction set program area 32 of its own, so that they can put the limited 32-bit bus width memory.
Thumb processor's first technique is provided ARM7TDMI. All ARM9 and later families, including XScale , have included Thumb technology.
Jazelle
ARM also developed a technology, Jazelle DBX (Direct Bytecode eXecution), allowing them to run faster on some architectures the Java bytecode , just as other operating modes like when you call a number not supported bytecodes special software, can provide accelerate the operation of certain bytecodes. It runs between each other in the existing ARM and Thumb mode.
The processor's first technique is provided Jazelle "ARM7EJ-S": Jazelle to a letter 'J' names marked on the CPU. It is used to allow handset manufacturers to accelerate the run Java ME games and applications, and thus contributed to the technology continues to develop.
Thumb-2
Thumb-2 technology first appeared in "ARM1156 core", and published in 2003. Thumb-2 extends the 16-bit Thumb instruction set is limited to the additional use of 32-bit instruction so that the instruction set wider. Thus it targets Thumb-2 is to reach almost the Thumb code density, but can exhibit properties near the ARM instruction set in the memory 32.
Thumb-2 so far from the ARM and Thumb instruction set derived from a variety of instructions, comprising a bit bar operations, operating conditions, and the branch table construction functions.
Thumb Execution Environment (ThumbEE)
ThumbEE, also known as Thumb-2EE, the industry known as Jazelle RCT technology, published in 2005, first appeared in the "Cortex-A8" processor. ThumbEE supplied from a number of scalability from Thumb-2, in which the operating environment, such that the instructions set to be particularly suitable for the operational phase of the code generator (e.g. time compiler ). Thumb-2EE is designed for a number of languages such as Limbo , the Java , C # , Perl and Python , and allows real-time compiler can output smaller compiled code without affecting the performance.
ThumbEE new features offered, including automatically checks each access command is invalid pointer, and an array bounds check instruction can be run, and can be branched to the classifier, which comprises a small part of the coding frequently called, commonly used to implement high-level language features, such as a new object to make memory configuration.
Advanced SIMD (NEON)
Advanced SIMD extension set, the industry as "NEON" technology, which is a combination of 64-bit and 128-bit single instruction multiple number of sets of instructions (SIMD), which have the ability to accelerate the standardization for multimedia and signal processing procedures. NEON can run on a processor of 10 MHz MP3 audio decoder, and may run the 13 MHz or less adaptive multi-rate audio compression coding. NEON having a broad set of instruction sets, each register array, and hardware run independently. NEON supports 8, 16 and 64-bit single precision floating point and integer data, and the number of single instruction multiple mode operation, run the graphics and game processing section on voice and video. Single instruction multiple instruction sets in a vector processor Super is a decisive element, which includes a number of simultaneous processing. In NEON art, SIMD 16 made up operation simultaneously.
VFP
VFP (vector floating point) is derived in a co-processor technology for the ARM architecture. It provides a low-cost single-precision and double-precision floating point capability, and is fully compatible with ANSI / IEEE Std 754-1985 Standard for Binary Floating Point Arithmetic . VFP provides floating-point operations suitable for most applications, such as PDA, smart phone, voice compression and decompression, 3D images and digital audio, printers, set-top boxes, and automotive applications. VFP architecture also supports SIMD parallel operation of the short instruction vector. This image and signal processing applications, very helpful to reduce code size and increase the output efficiency.
ARM-based processor, the other visible floating point, or the SIMD coprocessor further comprises a FPA, the FPE, iWMMXt . VFP they provide similar functionality, but opcode is not on the level of compatibility.
Reproduced in: https: //www.cnblogs.com/QuLory/archive/2012/10/23/2735142.html