The most detailed explanation of the whole network of FPGA GTP, aurora 8b/10b protocol, HDMI board-to-board video transmission, providing 2 sets of 4 sets of engineering source code and technical support

1 Introduction

I am ashamed to say that I have played FPGA before if I have never played GT resources. This is a sentence said by a big guy at CSDN, and I firmly believe it. . .
GT resources are an important selling point of Xilinx series FPGAs, and are also the basis for high-speed interfaces. Whether it is PCIE, SATA, MAC, etc., GT resources are required for high-speed data serialization and deserialization processing. Different FPGA series of Xilinx have different GT resource type, the low-end A7 has GTP, K7 has GTX, V7 has GTH, and the higher-end U+ series has GTY, etc. Their speed is getting higher and higher, and their application scenarios are becoming more and more high-end. . .

This article uses the GTP resources of Xilinx's Artix7 FPGA to do board-to-board video transmission experiments. The video source uses a laptop to output an analog HDMI video input, calls the GTP IP core, and uses verilog to write the codec module and data alignment module of video data. Using the development Two SFP optical ports on the board hardware realize data transmission and reception; this blog provides two sets of vivado project source codes, the difference between the two sets of projects is that two FPGA development boards are used for receiving and sending respectively; this blog describes the FPGA GTP video in detail The transmission design scheme, the engineering code can be comprehensively compiled and debugged on the board, and can be directly ported to the project. It is suitable for the development of students and postgraduate projects, and it is also suitable for the learning and improvement of in-service engineers. It can be applied to high-speed interfaces in medical, military and other industries. In the field of image processing;
provide complete and smooth project source code and technical support;
the method of obtaining project source code and technical support is at the end of the article, please be patient to read the end;

disclaimer

This project and its source code are partly written by myself, and partly obtained from public channels on the Internet (including CSDN, Xilinx official website, Altera official website, etc.). The project and its source code are limited to the personal study and research of readers or fans, and commercial use is prohibited. If the legal issues caused by the commercial use of readers or fans for their own reasons have nothing to do with this blog and the blogger, please use it with caution. . .

2. The GT high-speed interface solution I have here

My homepage has a FPGA GT high-speed interface column, which includes video transmission routines and PCIE transmission routines for GT resources such as GTP, GTX, GTH, and GTY, among which GTP is based on A7 series FPGA development boards, and GTX is based on K7 or ZYNQ series FPGA development board is built, GTH is built based on KU or V7 series FPGA development board, GTY is built based on KU+ series FPGA development board; the following is the column address:
click to go directly

3. The most detailed interpretation of the GTP network

The most detailed introduction to GTP must be Xilinx's official "ug482_7Series_GTP_Transceivers", we use this to interpret:
I have put the PDF document of "ug482_7Series_GTP_Transceivers" in the information package, and there is a way to obtain it at the end of the article; the
FPGA model of the development board I used It is Xilinx Artix7 xc7a35tfgg484-2; it has 4 channels of GTP resources, and the sending and receiving speed of each channel is between 500 Mb/s and 6.6 Gb/s. GTP transceivers support different serial transmission interfaces or protocols, such as PCIE 1.1/2.0 interface, 10 Gigabit network XUAI interface, OC-48, serial RapidIO interface, SATA (Serial ATA) interface, digital component serial interface (SDI) etc;

GTP basic structure

Xilinx uses Quad to group serial high-speed transceivers. Four serial high-speed transceivers and a COMMOM (QPLL) form a Quad. Each serial high-speed transceiver is called a Channel (channel). The figure below shows four The schematic diagram of the GTP transceiver in the Artix-7 FPGA chip: "ug482_7Series_GTP_Transceivers" page 13; the

specific internal logic block diagram of GTP is shown below, which consists of four transceiver channels GTPE2_CHANNEL primitives and a GTPE2_COMMON primitive. Each GTPE2_CHANNEL includes a transmitting circuit TX and a receiving circuit RX; "ug482_7Series_GTP_Transceivers" page 14; the

logic circuit of each GTPE2_CHANNEL is shown in the following figure: "ug482_7Series_GTP_Transceivers" page 15;

the functions of the transmitting end and receiving end of GTPE2_CHANNEL are independent, both It consists of two sublayers: PMA (Physical Media Attachment, physical media adaptation layer) and PCS (Physical Coding Sublayer, physical coding sublayer). The PMA sublayer includes high-speed serial-to-parallel conversion (Serdes), pre-/post-emphasis, receiving equalization, clock generator and clock recovery circuits. The PCS sublayer includes circuits such as 8B/10B codec, buffer, channel bonding, and clock correction.
It doesn’t make much sense to say too much here, because if you haven’t done a few big projects, you won’t understand what’s inside. For first-time users or fast users, more energy should be focused on the calling and use of IP cores , I will also focus on the call and use of the IP core later;

GTP send and receive processing flow

First, the user logic data enters a sending buffer (Phase Adjust FIFO) after being encoded by 8B/10B. This buffer is mainly used for clock isolation between the two clock domains of the PMA sublayer and the PCS sublayer, and solves the clock rate matching and phase adjustment between the two. For the problem of difference, the parallel-to-serial conversion (PISO) is performed through high-speed Serdes. If necessary, pre-emphasis (TX Pre-emphasis) and post-emphasis can be performed. It is worth mentioning that if you accidentally cross-connect the TXP and TXN differential pins during PCB design, you can make up for this design error through polarity control (Polarity). The receiving end and the sending end process are opposite, and there are many similarities, so I won’t go into details here. It should be noted that the elastic buffer of the RX receiving end has clock correction and channel binding functions. Every function point here can write a paper or even a book, so here you only need to know a concept, and you can use it in a specific project, or the same sentence: For the first time or want to use it quickly For those who are concerned, more energy should be focused on the calling and use of IP cores.

Reference clock for GTP

The GTP module has two differential reference clock input pins (MGTREFCLK0P/N and MGTREFCLK1P/N), which can be selected by the user as the reference clock source of the GTP module. On the general A7 series development board, there is a 125Mhz GTP reference clock connected to MGTREFCLK0/1 as the GTP reference clock. The differential reference clock is converted into a single-ended clock signal by the IBUFDS module and entered into PLL0 and PLL1 of GTPE2_COMMOM to generate the required clock frequency in the TX and RX circuits. If the TX and RX transceiver speeds are the same, the TX circuit and the RX circuit can use the clock generated by the same PLL. If the TX and RX transceiver speeds are not the same, the clocks generated by different PLL clocks need to be used. Reference clock Here, the GT reference routine given by Xilinx has been done very well, and we don’t need to modify it when we call it; the reference clock structure of GTP is as follows: "ug482_7Series_GTP_Transceivers" page 21;

GTP send interface

Pages 75 to 123 of "ug482_7Series_GTP_Transceivers" introduce the transmission process in detail, and most of the content can be ignored by users, because the manual basically talks about his own design ideas, leaving the user's operable interface and Not many, based on this idea, we will focus on the interfaces that are required for the sending part left to the user during GTP instantiation;

users only need to care about the clock and data of the sending interface. The interface of this part of the GTP instantiation module is as follows:


In the code, I have rebinded for you and made it to the top level of the module, the code part is as follows:

GTP receiving interface

Pages 125 to 213 of "ug482_7Series_GTP_Transceivers" introduce the transmission process in detail, and most of the content can be ignored by users, because the manual basically talks about his own design ideas, leaving the user's operable interface and Not many, based on this idea, we will focus on the interfaces that are required for the sending part left to the user during GTP instantiation;

users only need to care about the clock and data of the receiving interface. The interface of this part of the GTP instantiation module is as follows:


In the code, I have rebinded for you and made it to the top level of the module, the code part is as follows:

GTP IP core call and use

Different from the tutorials of other bloggers on the Internet, I personally like to use the shared logic as shown in the figure below:

There are two advantages of this choice, one is to facilitate DRP speed change, and the other is to facilitate the modification of the IP core. After modifying the IP core, compile it directly. But, it is no longer necessary to open the example project, and then copy a bunch of files below into your own project or something. Does it need to be so complicated to play GTP?

Here is an explanation of the labels in the above picture:
1: Line rate, according to your own project requirements, the range of GTP is 0.5 to 6.25G. Since my project is video transmission, it can be within the range of GTP rate, for general use Specifically, I instantiated 5 GTPs in the vivado project, and the rates are 1G, 2G, 4G, 5G; 2:
Reference clock, this depends on your schematic diagram, it can be 80M, 125M, 148.5M, 156.25M Wait, my development board is 125M;
4: GTP group binding, this is very important, there are two binding references, it is your development board schematic diagram, but the official reference "ug482_7Series_GTP_Transceivers" , the official GTP resources are divided into 4 groups, the names are X0Y0, X0Y1, X0Y2, X0Y3. Since GT resources are dedicated resources for Xilinx series FPGAs and occupy dedicated Bnak, the pins are also dedicated. Then these GTP groups and boots How do the feet correspond? The description of "ug482_7Series_GTP_Transceivers" is as follows: the red box is the FPGA pin corresponding to the schematic diagram of my development board; the
schematic diagram of my board is as follows:


select the 8b/10b codec with an external data bit width of 32bit, as follows

: It is K code detection:

choose K28.5 here, which is the so-called COM code, and the hexadecimal system is bc. It has many functions, and it can represent idle disordered symbols and data misalignment marks. It is used to mark data misalignment. , the 8b/10b protocol defines the K code as follows:

The following is clock correction, that is, the elastic buffer corresponding to the internal receiving part of GTP;

here is a concept of clock frequency offset, especially when the clock sources of the sending and receiving parties are different, the frequency offset here is set to 100ppm, and it is stipulated that every 5000 data The sender of the packet sends a 4-byte sequence, and the elastic buffer of the receiver will decide to delete or insert a byte in the 4-byte sequence according to the 4-byte sequence and the position of the data in the buffer. It is to ensure the stability of data from the sending end to the receiving end and eliminate the influence of clock frequency offset;

4. Design thinking framework

This blog provides 2 sets of vivado project source codes. The difference between the 2 sets of projects is that two FPGA development boards are used for receiving and sending respectively; I have 2 FPGA development boards here, which are recorded as development board 1 and development board 2. There are HDMI input and output interfaces on the board. The source codes of the 2 groups of vivado projects are as follows:
The first group of vivado project source codes: Laptop analog video source input to the HDMI input interface of the development board 1, through the GTP encoding of this board, and the SFP of this board The TX interface of the optical port sends out; the RX interface of the SFP optical port of the development board 2 receives data, decodes it through the GTP of this board, and then buffers the image for three frames, and then sends the HDMI video to the display through the HDMI sending module; the block diagram is as follows

: 2 groups of vivado project source codes: Laptop analog video source input to HDMI input interface of development board 2, encoded by GTP of this board, sent out through TX interface of SFP optical port of this board; RX interface of SFP optical port of development board 1 After receiving the data, it is decoded by the GTP of this board, and then the image is cached for three frames, and then the HDMI video is sent to the display through the silcom9134 chip; the block diagram is as follows:

HDMI input video configuration and capture

The HDMI input decoding of the first group of vivado project source code is completed by silcom9011 chip; the HDMI input decoding of the second group of vivado project source code is completed by ADV7611 chip; both of them need i2c configuration to be used, and both are i2c configuration realized by pure verilog code The module is completed;
for the configuration of the silicon9011 chip, please refer to my previous blog, blog address: click to go directly

video packet

Since the video needs to be sent and received through the aurora 8b/10b protocol in GTP, the data must be packaged to adapt to the aurora 8b/10b protocol standard; the code position of the video data package module is as follows: first, we store the 16bit video in the

FIFO , when a row is full, it is read from FIFO and sent to GTP for transmission; before that, a frame of video needs to be numbered, which is also called an instruction. When GTP packs, it sends data according to a fixed instruction. The command restores the video field synchronization signal and video effective signal; when the rising edge of a frame of video field synchronization signal arrives, send a frame of video start instruction 0, and when the falling edge of a frame of video field synchronization signal arrives, send a frame Video start command 1, send invalid data 0 and invalid data 1 during the video blanking period, number each line of video when the video valid signal arrives, first send a line of video start command, and then send the current video line number, when a line of video is sent After completion, send a line of video end command. After sending a frame of video, first send a frame of video end command 0, and then send a frame of video end command 1; so far, a frame of video is sent. This module is not easy to understand. So I made detailed Chinese comments in the code. It should be noted that in order to prevent the disordered display of Chinese comments, please open the code with notepad++ editor; the command definition is as follows: the command can be changed arbitrarily, but the lowest byte must be

bc ;

GTP aurora 8b/10b

This is to call GTP to do the data encoding and decoding of the aurora 8b/10b protocol. I have already made a detailed overview of GTP, so I won’t talk about it here; 2G, 4G, 5G; the code uses a parameter to select the rate, as follows:

GTP_RATE=8'd1, GTP runs at 1G line rate;
GTP_RATE=8'd2, GTP runs at 2G line rate;
GTP_RATE=8'd4, GTP runs at 2G line rate; Run at 4G line rate;
GTP_RATE=8'd5, GTP runs at 5G line rate;
According to my test, the video transmission effect is best when GTP runs at 4G line rate;

data alignment

Since the aurora 8b/10b data transmission and reception of GT resources naturally has data misalignment, it is necessary to perform data alignment processing on the received decoded data. The code position of the data alignment module is as follows: The K code control character format I defined is: XX_XX_XX_BC, so

use One rx_ctrl indicates whether the data is a K-code COM symbol;
rx_ctrl = 4'b0000 indicates that the 4-byte data has no COM code;
rx_ctrl = 4'b0001 indicates that [7: 0] in the 4-byte data is a COM code;
rx_ctrl = 4'b0010 means [15: 8] in the 4-byte data is the COM code;
rx_ctrl = 4'b0100 means the [23:16] in the 4-byte data is the COM code;
rx_ctrl = 4'b1000 means the 4-byte [31:24] in the data is the COM code;
based on this, when the K code is received, the data will be aligned, that is, the data will be patted, and the new data will be misplaced and combined. This is the basis of FPGA Operation, no more details here;

Video data unpacking

Data unpacking is the reverse process of data grouping, and the code position is as follows:

When GTP unpacks, restore the video field synchronization signal and video effective signal according to fixed instructions; these signals are important signals for the subsequent image cache;
so far, the data enters and exits GTP The part has been finished, and the block diagram of the whole process is described in the code, as follows:

image cache

Old fans who often read my blog should know that my routine for image caching is FDMA. Its function is to send images to DDR for 3 frame buffers and then read them out for display. The purpose is to match the clock difference between input and output and improve output. Video quality, about FDMA, please refer to my previous blog, blog address: click to go directly

video output

The HDMI output of the first group of vivado project source code is completed by the handwritten HDMI transmission module of verilog code, which can be used in the HDMI transmission application of FPGA. For this module, please refer to my previous blog. Blog address: click to go directly to the second group of vivado
project The HDMI output of the source code is completed by silcom9134. Silcom9134 needs i2c configuration to be used. It is completed by the i2c configuration module implemented by pure verilog code;
for the configuration of the silcom9134 chip, please refer to my previous blog, blog address: click to go directly

5. Detailed explanation of the first group of vivado projects

HDMI video GTP sending project of development board 1

Development board FPGA model: Xilinx–Artix7–xc7a35tfgg484-2;
development environment: Vivado2019.1;
input: HDMI video of development board 1, resolution 1920x1080@60Hz;
output: TX interface of SFP optical port of development board 1;
application: HDMI board-to-board video transmission;
the engineering code structure is as follows:

FPGA resource consumption and power consumption estimation after comprehensive compilation is as follows:

GTP receiving HDMI display project of development board 2

Development board FPGA model: Xilinx–Artix7–xc7a35tfgg484-2;
development environment: Vivado2019.1;
input: the RX interface of the SFP optical port of development board 2; output
: the HDMI transmission interface of development board 2 to send to the display;
application: HDMI board pair Board video transmission;
the project Block Design is as follows:

the project code structure is as follows:

FPGA resource consumption and power consumption estimation after comprehensive compilation is as follows:

6. Detailed explanation of the second group of vivado projects

HDMI video GTP sending project of development board 2

Development board FPGA model: Xilinx–Artix7–xc7a35tfgg484-2;
development environment: Vivado2019.1;
input: HDMI video of development board 1, resolution 1920x1080@60Hz;
output: TX interface of SFP optical port of development board 2;
application: HDMI board-to-board video transmission;
the engineering code structure is as follows:

FPGA resource consumption and power consumption estimation after comprehensive compilation is as follows:

GTP receiving HDMI display project of development board 1

Development board FPGA model: Xilinx–Artix7–xc7a35tfgg484-2;
development environment: Vivado2019.1;
input: the RX interface of the SFP optical port of development board 1;
output: the HDMI transmission interface of development board 1 to send to the display;
application: HDMI board pair Board video transmission;
the project Block Design is as follows:

the project code structure is as follows:

FPGA resource consumption and power consumption estimation after comprehensive compilation is as follows:

7. Board debugging and verification

fiber optic connection

The optical fiber connections of the two boards of the first group of vivado projects are as follows:

static demo

The following takes the two boards of the first group of vivado projects as an example to show the output effect:
when GTP runs at 4G line rate, the output is as follows:

dynamic presentation

The short video of the two boards of the first group of vivado projects is as follows;

GTP-HDMI board-to-board video transmission 1

8. Benefits: Acquisition of engineering codes

Benefits: Obtaining the engineering code
The code is too large to be sent by email, and it is sent by a certain degree network disk link. The
method of data acquisition: private, or the V business card at the end of the article.
The network disk information is as follows: