【STM32】Basic timer

Learn based on stm32f103
based on "Playing with STM32 with Zero Dead Angle—F103 Guide"

timer

Classification

Basic timer, general timer, advanced timer

Functional block diagram

Simply put, the clock from APB or AHB passes through PSC (divided from 1 to 65535) to form a time base. Each time it passes through a time base, TIM's cnt count is once. According to the configuration of the register, update events, comparison events, etc. occur. .

Clock source (when the prescaler is not 1, it needs to be multiplied by 2)

1. The basic timer clock is mounted on the APB1 bus, so its clock comes from the APB1 bus .
2. It is not provided directly by the APB1 bus, but first passes through a frequency multiplier .
  When the prescaler coefficient of APB1 is 1, this multiplier coefficient is 1.
  When the prescaler coefficient of APB1 is ≥2, the frequency multiplier coefficient is 2, that is, the timer clock frequency is equal to twice the APB1 bus clock frequency.
  The prescaler here refers to the frequency division of APB1, not the PSC prescaler
3 above. The steps for prescaling APB1 are generally in the systeminit function, that is, in the startup file, the reset_handle() function started in. Generally speaking, the library function automatically sets it for us. The APB1 prescaler coefficient in the library function is 2, that is, PCLK1=36M, so the timer clock TIMxCLK=36*2=72M.

TIM's prescaler is writable at runtime and is enabled after an update event occurs

1. Prescaler can divide the counter clock by any value between 1 and 65536.
2. This PSC can be changed during operation, but its effectiveness will be recorded in the CNT counter to the next update event.
Counter timing diagram when the prescaler coefficient changes from 1 to 2

Counter CNT

1. Start counting according to the frequency division.
2. Accumulate counting from 0 to the automatic reload value (TIMx_ARR register), and then restart counting and generate a counter overflow event.
3. An update event can be generated each time the counter overflows; an update event can also be generated by setting the UG bit of the TIMx_EGR register (through software or using a slave mode controller).

Auto-reload register

The automatic reload register ARR is a 16-bit register, which contains the maximum value that the counter can count. When counting to this value, if the interrupt is enabled, the timer will generate an overflow interrupt.

example

Basic timer configuration

 void BASIC_TIM_Config(void)
{
    
    
	TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;

	// 开启定时器时钟,即内部时钟 CK_INT=72M
	BASIC_TIM_APBxClock_FUN(BASIC_TIM_CLK, ENABLE);

	// 自动重装载寄存器周的值(计数值)
	TIM_TimeBaseStructure.TIM_Period=1000;
 
	 // 累计 TIM_Period 个频率后产生一个更新或者中断
	 // 时钟预分频数为 71，则驱动计数器的时钟 CK_CNT = CK_INT / (71+1)=1M
	 TIM_TimeBaseStructure.TIM_Prescaler= 71;
	 // 时钟分频因子 ，基本定时器没有，不用管
	 //TIM_TimeBaseStructure.TIM_ClockDivision=TIM_CKD_DIV1;

	 // 计数器计数模式，基本定时器只能向上计数，没有计数模式的设置
	 //TIM_TimeBaseStructure.TIM_CounterMode=TIM_CounterMode_Up;

	 // 重复计数器的值，基本定时器没有，不用管
	 //TIM_TimeBaseStructure.TIM_RepetitionCounter=0;

	 // 初始化定时器
	 TIM_TimeBaseInit(BASIC_TIM, &TIM_TimeBaseStructure);

	 // 清除计数器中断标志位
	 TIM_ClearFlag(BASIC_TIM, TIM_FLAG_Update);

	 // 开启计数器中断
	 TIM_ITConfig(BASIC_TIM, TIM_IT_Update, ENABLE);

	 // 使能计数器
	 TIM_Cmd(BASIC_TIM, ENABLE);

	 // 暂时关闭定时器的时钟，等待使用
	 BASIC_TIM_APBxClock_FUN(BASIC_TIM_CLK, DISABLE);
 }

Interrupt priority configuration

void BASIC_TIM_NVIC_Config(void)
{
    
    
NVIC_InitTypeDef NVIC_InitStructure;
// 设置中断组为 0
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
// 设置中断来源
NVIC_InitStructure.NVIC_IRQChannel = BASIC_TIM_IRQ ;
// 设置主优先级为 0
 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
 // 设置抢占优先级为 3
 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
 NVIC_Init(&NVIC_InitStructure);
}