table of Contents

4.3, center alignment (up/down counting mode)

The most basic function of a timer is to process things regularly. For example, send USART data regularly, collect AD data regularly, detect the potential of the IO port regularly, and output waveforms through the IO port. Can realize very rich function. Timer is a very powerful peripheral. Different industries use it in different ways and have a wide range of knowledge.

01. Timer introduction

First of all, we can find the resources of the customizer in the STM32F207 data manual. From the figure below, you can see that STM32F207 has a total of 10 general-purpose timers, 2 advanced timers, and 2 basic timers.

The difference between different timers

You can see the basic block diagram of the timer in the user reference manual of the STM32F207. The following figure shows the timer 1&8.

It can be seen from the above figure that different registers have different parameters, the difference in digits, the difference in counting mode, the difference in DMA request, the difference in channel, the difference in complementary output and others. Which timer to choose in a specific project depends on specific application scenarios. The following mainly explains the basic timing function of the timer, select Timer 3. The principles of other timers are the same. If you understand the timing function of Timer 3, you can understand other timers. For the STM32 series of single-chip microcomputers, the peripherals are basically the same, and the MCUs of other families are also similar, such as Zhaoyi Innovation, Nuvoton Technology, Shanghai Smart Microelectronics and so on.

02, clock source

The basic timing function block diagram of the timer.

①CK_PSC is the timer clock TIMxCLK, which is divided by the APB1 prescaler and provided.

②After the timer clock passes through the PSC prescaler, that is, CK_CNT, it is used to drive the counter to count.

③Counter CNT is a 16-bit counter, up, down, up/down counting mode, the maximum count value is 65535. When the count reaches the automatic reload register, an update event is generated, and the count is reset from the beginning.

④ The automatic reload register ARR is a 16-bit register, which contains the maximum value that the counter can count. When the count reaches this value, if the interrupt is enabled, the timer will generate an overflow interrupt.

To put it bluntly, the timer is a counter, just like we use the heartbeat to roughly estimate the time, the heartbeat can be roughly regarded as 1s, then we count 60 heartbeats and 60 seconds have passed. The CK_CNT clock is similar to the heartbeat, and the CNT counter is similar to the number of heartbeats. To give an extremely simple example, we want to achieve a 60-second timing, CK_CNT is 1s, we set the CNT counter to count up to turn on the interrupt, because there will be an interrupt only when it overflows, that is, when the count reaches 65535, then we set the CNT counter to 65535 -60=65475, start in time, then an interrupt will be generated after 60 seconds. We set the auto-reload register ARR to 65475. When the CNT counter overflows, the auto-reload register ARR will be automatically loaded into the CNT counter, which can realize automatic cycle timing for 60 seconds.

After the above analysis, the key to accurate timing lies in the frequency of CK_CNT, and CK_CNT is derived from the frequency division of the timer clock. Then we need to know the timer clock of timer3. We have to look at the clock system part, specifically see the article " STM32F207 clock system analysis ", this article mainly explains how the system's 120M clock is obtained from an external 25M crystal oscillator. It talks about the APB peripheral clock problem.

The timer is under the APB timer clock, specifically under the APB1 or APB2 clock, we can see from the STM32F207 data sheet, the picture name is STM32F20xblock diagram.

From the above we see that timer3 is under APB1.

So let’s analyze the frequency of APB1

It can be seen from the above figure that the slave system 120M clock of the APB1 timer (the system clock is configurable, we use the default 120M clock) is obtained by AHB frequency division and APB frequency division.

Mengxin may not understand the "error" in the red box above. First of all, a closing bracket is missing in the manual. After modification, it should read:

if(APBx presc == 1)
    X1
else
    X2

In other words

If the APB frequency division coefficient is 1, the frequency remains unchanged, and the frequency output by the APB is the frequency of the clock below the APB.

APB frequency division factor is not 1, frequency X2, APB output frequency multiplied by 2 is the frequency of the clock below APB.

Below we analyze the APB1 clock, from the SetSysClock function in system_stm32f2xx.c as follows

/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
    
/* PCLK2 = HCLK / 2*/
RCC->CFGR |=RCC_CFGR_PPRE2_DIV2;
    
/* PCLK1 = HCLK / 4*/
RCC->CFGR|= RCC_CFGR_PPRE1_DIV4;

It can be seen that the AHB frequency division coefficient is 1, and the APB1 frequency division coefficient is 4.

The clock of timer3 is 120M/1/4*2=60MHZ.

There is a question here. Why the system_stm32f2xx.c comment provided by ST is HCLK, PCLK2, PCLK1, but there is no APB, AHB mentioned above. For details, see the article " STM32F207 Clock System Analysis " I wrote before .

In fact, we have published the analysis code, and the header of the system_stm32f2xx.c file is also annotated for easy viewing.

Of course, this requires our external crystal oscillator to be 25M, and system_stm32f2xx.c has not been modified. If you need to modify this file for MCU overclocking operation, it is recommended to modify the comments in the file header to develop a good habit.

03. Time base unit

The programmable advanced timer control module is mainly a 16-bit counter with related automatic reload. This counter can count up, count down, or alternately count up and down. The counter clock can be divided by a frequency divider.

The automatic reload register and prescaler register of the counter can be read and written by software. It can be read and written even when the counter is running.

Time base unit includes

Counter register (TIMx_CNT)
Prescaler register (TIMx_PSC)
Auto reload register (TIMx_ARR)
Repeat counter register (TIMx_RCR)

The auto-reload register is preloaded. Writing or reading from the auto-reload register will access the preload register. The content of the preload register can be directly transferred to the shadow register, or it can be transferred to the shadow register every time an update event (UEV) occurs, depending on the automatic reload preload enable bit (ARPE) in the TIMx_CR1 register . When the counter reaches the overflow value (or reaches the underflow value when counting down) and the UDIS bit in the TIMx_CR1 register is 0, an update event will be sent. The update event can also be generated by software.

The counter is clocked by the prescaler output CK_CNT, and the counter is started only when the counter enable bit (CEN) in the TIMx_CR1 register is set to 1.

Prescaler description

The prescaler can divide the counter clock frequency with a division factor between 1 and 65536. The prescaler is based on a 16-bit counter controlled by the 16-bit register in the TIMx_PSC register. Because the control register has a buffer function, the prescaler can be changed in real time. The new prescaler ratio will be adopted when the next update event occurs.

The following figure illustrates the behavior of the counter when the prescaler ratio changes in real time with some examples.

The timing diagram of the counter when the prescaler divides from 1 to 2

The timing diagram of the counter when the prescaler divides from 1 to 4

04. Counting mode

4.1, up counting mode

In the up-counting mode, the counter increases from 0 to the auto-reload value (the value of the TIMx_ARR register), and then restarts from 0 and generates a counter overflow event.

If a repeat counter is used, when the number of repetitions of the increment count reaches the number programmed in the repeat counter register plus one (TIMx_RCR+1), an update event (UEV) will be generated. Otherwise, an update event will be generated every time the counter overflows.

When setting the UG bit of the TIMx_EGR register to 1 through software or using a slave mode controller, an update event will also be generated.

The UEV event can be disabled by software setting the UDIS bit in the TIMx_CR1 register to 1. This avoids updating the shadow register when a new value is written to the preload register. No update event will be generated until the UDIS bit is written to 0. However, both the counter and the prescaler counter will restart counting from 0 (while the prescaler ratio remains unchanged). In addition, if the URS bit (update request selection) in the TIMx_CR1 register is set to 1, setting the UG bit to 1 will generate an update event UEV, but will not set the UIF flag (thus, no interrupt or DMA request will be sent). In this way, if the counter is cleared when a capture event occurs, the update interrupt and the capture interrupt will not be generated at the same time.

When an update event occurs, all registers will be updated and the update flag (UIF bit in the TIMx_SR register) will be set to 1, depending on the URS bit)

The contents of the TIMx_RCR register will be reloaded in the repeat counter
The auto-reload shadow register will be updated with the preload value (TIMx_ARR)
The pre-load value (contents of the TIMx_PSC register) will be reloaded in the buffer of the prescaler

Counter timing diagram, divided by 1 internal clock

Counter timing diagram, divided by 2 internal clock

It can be seen from the above two figures that the interrupt flag needs to be cleared by software

Counter timing diagram, update event when ARPE=0 (TIMx_ARR is not preloaded)

It can be seen from the above two figures that when counting up, before reaching 0x36, modify the auto-reload register to 0x36, and an action will occur when the count reaches 0x36.

Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

It can be seen from the above two figures that when counting upwards, before reaching 0x36, modify the auto-reload preload register to 0x36, and there will be no action when the count reaches 0x36, and the preload will be automatically reloaded at this time The register value is assigned to the automatic reload shadow register.

4.2, down counting mode

In the down-counting mode, the counter counts down from the auto-reload value (TIMx_ARR register value) to 0, and then from the auto-reload value (restarts and generates a counter overflow event.

If a repeat counter is used, when the number of repetitions of the countdown reaches the number programmed in the repeat counter register plus one (TIMx_RCR+1), an update event (UEV) will be generated. Otherwise, an update event will be generated every time the counter underflows.

When the UG bit of the TIMx_EGR register is set to 1 (by software or using a slave mode controller), an update event will also be generated.

The UEV update event can be disabled by setting the UDIS bit in the TIMx_CR1 register to 1 by software. This avoids updating the shadow register when a new value is written to the preload register. No update event will be generated until the UDIS bit is written to 0. However, the counter will restart counting from the current auto-reload value, and the prescaler counter will restart counting from 0 (but the prescaler ratio remains unchanged).

In addition, if the URS bit (update request selection) in the TIMx_CR1 register has been set to 1, setting the UG bit to 1 will generate an update event UEV, but will not set the UIF flag (thus, no interrupt or DMA request will be sent). In this way, if the counter is cleared when a capture event occurs, the update interrupt and the capture interrupt will not be generated at the same time.

When an update event occurs, all registers will be updated and the update flag (UIF bit in the TIMx_SR register) will be set to 1 (depending on the URS bit):

The contents of the TIMx_RCR register will be reloaded in the repeat counter
The buffer of the prescaler will be reloaded with the preload value (contents of the TIMx_PSC register)
The auto-reload activity register will be updated with the preload value (contents of the TIMx_ARR register). Note that the auto-reload register will be updated before the counter is reloaded, so the next counting cycle is the new cycle length we want

The following figures illustrate the behavior of the counter under different clock frequencies with some examples when TIMx_ARR=0x36

Counter timing diagram, divided by 1 internal clock

Counter timing diagram, divided by 2 internal clock

Counter timing diagram, update event when repeat counter is not used

4.3, center alignment ( up / down counting mode )

In the center-aligned mode, the counter starts counting from 0 to the automatic reload value (the contents of the TIMx_ARR register) -1, and generates a counter overflow event; then, starts counting down from the automatic reload value to 1 and generates a counter underflow event. Then start counting from 0 again.

When the CMS bit in the TIMx_CR1 register is not "00", the center-aligned mode is valid. When the channel is configured in output mode, its output compare interrupt flag will be set to 1 in the following modes, namely: counter count down (center-aligned mode 1, CMS = "01"), counter count up (center-aligned mode 2, CMS = "10") and the counter up/down count (center alignment mode 3, CMS = "11").

In this mode, the DIR direction bit of the TIMx_CR1 register cannot be written with a value, but is updated by the hardware and indicates the current counter direction.

An update event is generated every time a counter overflow and underflow occurs, or an update event can be generated by setting the UG bit in the TIMx_EGR register to 1 (by software or using a slave mode controller). In this case, the counter and prescaler counter will start counting from 0 again.

The UEV update event can be disabled by setting the UDIS bit in the TIMx_CR1 register to 1 by software. This avoids updating the shadow register when a new value is written to the preload register. No update event will be generated until the UDIS bit is written to 0. However, the counter will still count up and down according to the current auto-reload value.

In addition, if the URS bit (update request selection) in the TIMx_CR1 register has been set, setting the UG bit to 1 will generate a UEV update event, but will not set the UIF flag (thus, no interrupt or DMA request will be sent). In this way, if the counter is cleared when a capture event occurs, the update interrupt and the capture interrupt will not be generated at the same time.

When an update event occurs, all registers will be updated and the update flag (UIF bit in the TIMx_SR register) will be set to 1 (depending on the URS bit):

The contents of the TIMx_RCR register will be reloaded in the repeat counter
The buffer of the prescaler will be reloaded with the preload value (contents of the TIMx_PSC register)
The auto-reload activity register will be updated with the preload value (contents of the TIMx_ARR register). Note that if the update operation is triggered by a counter overflow, the auto-reload register is updated before the counter is reloaded. Therefore, the next counting cycle is the new cycle length we want (the counter is reloaded with a new value).

The following figures illustrate the behavior of the counter under different clock frequencies with some examples

Counter timing diagram, divided by 1 internal clock, TIMx_ARR = 0x6

Counter timing diagram, divided by 2 internal clock

Counter timing diagram, update event when ARPE=1 (counter underflow)

Counter timing diagram, update event when ARPE=1 (counter overflow)

05, basic timing code

10ms interrupt configuration code

About setting the divide value

TIM3CLK = 2 * PCLK1=2*HCLK / 4= HCLK / 2 = SystemCoreClock /2=60MHZ

So the red box in the figure below is TIM3CLK

The value here is the frequency division factor = TIM3CLK/timer actual frequency, so the timer frequency is 10000, which means that the divisor is the timer frequency. A clk is 1/10000s. Timing time=1/10000*timer reload value. According to the above configuration, the timer reload value is 100, that is, the timer interrupt period is=1/10000*100=0.01s=10ms, which is 100HZ.

If the LED light is flipped on the timer, the flashing frequency of the LED light is 50 Hz.

Of course, the above frequency divider value can be directly assigned to 5999. If you want to modify the timer frequency to 1000, you need to recalculate it. If you follow the above writing method, you can directly modify the divisor to 1000.

When you see this, everyone will have questions. The given overload value is obviously 99, and the division frequency value is also subtracted by 1. The following will explain the reason why both the frequency division value and the auto reload period value need to be subtracted by 1.

Automatic reload value: Because the calculation starts from 0, the value is assigned to 10, and the count from 0 to 10 is 11 times.

Divider value: There are the following descriptions in the TIMx_PSC register.

Special Note

Clock division factor

TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV2;

In fact, after reading the technical manual carefully, I found that this sentence has nothing to do with the PWM output experiment. This sentence is the division between the frequency of the timer clock (CK_INT) and the sampling frequency used by the digital filter (ETR, TIx) Proportional (related to input capture), 0 means that the frequency of the filter is the same as the frequency of the timer.

First, the colck_division clock division factor does not divide the clock frequency of the timer. We all know that there is a digital filter in the input capture mode. This digital filter can change its sampling frequency through the configuration register to filter out some frequencies.

The specific details are explained in the input capture.

We can also use the method of querying the counter to achieve precise delay according to the characteristics of the timer's counter. For details, please see " Four Methods of STM32 Delay Function ".

Timer code open source address:

https://github.com/strongercjd/STM32F207VCT6

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Detailed STM32 basic timer

01. Timer introduction

02, clock source

03. Time base unit

04. Counting mode

4.1, up counting mode

4.2, down counting mode

4.3, center alignment ( up / down counting mode )

05, basic timing code

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