Explanation of digital tube dynamic display routine
1. Interpretation of requirements
1.1 Requirements
Stable display of 123456 on the six-digit digital tube
1.2 Knowledge background
The digital tube is an "8"-shaped device composed of multiple LED light-emitting diodes. According to different polarities, it is divided into common anode and common cathode. Our development board uses a common anode digital tube. The internal structure of the digital tube is as shown below:
As can be seen from the figure, the difference between common anode and common cathode. The common terminal of the common anode is connected to the positive terminal of the power supply, and the common terminal of the common cathode is connected to the ground. When choosing a common anode digital tube, we only need to set the corresponding abcdefgdq to a low level to light up the corresponding digital tube. On the contrary, the common cathode needs to connect abcdefgdq to the positive pole of the power supply to light up the corresponding digital tube. The schematic diagram of the digital tube is as follows:
The development board we chose uses a common anode digital tube. If we want to display 2, then we should light up the A, B, G, E, and D LEDs. If you want to display 5, you can analyze by yourself which segments should be lit, so that we can get the codes from 0 to 9 of the common yang digital tube. In order to save everyone's time, I have sorted out the codes corresponding to the common Yang digital tube, as shown below, which can be called directly. The coding of the common cathode digital tube only requires bitwise inversion.
Our development board common yang digital tube segment selection coding table is as follows:
1.3 Hardware design
We use a PNP transistor on the development board. When a low level is input to the base of the transistor, the collector and emitter of the transistor are connected, and a voltage of 3.3V is applied to the bit selection pin of the digital tube. Then we To light up the first digital tube, you need to input low level to SMG_W0, and assign values to the segment selection of the digital tube according to the digital tube coding table. Now that the principle is mastered, we can start writing code
1.4 Principle of dynamic scanning of digital tube
We talked about the static display of the digital tube in the previous lecture. If there is only one bit, using static scanning, we need to control 8 segment selections and 1 bit selection, for a total of 9 pins. If we want to control a 6-digit digital tube and use the same static display method, a total of 9*6=54 pins will be used, which will inevitably cause a serious waste of pins. In order to save pins and display multiple bits of information at the same time, we can use dynamic scanning to drive multi-digit digital tubes. In the same way we drive 6-bit digital tubes, we only need to control 8 segment selections and 6 digital tubes using dynamic scanning. The bit selection signal has a total of 14 pins, which saves 40 pins compared with static scanning. Therefore, using dynamic scanning to drive the digital tube is something we must learn in study and work. Multi-digit digital tubes are used to display more numerical information. They are composed of multiple digital tubes. The segments (a~h) of these digital tubes are connected together in a one-to-one correspondence, and the common pole is independent. Dynamic scanning selects the digital tubes one by one in a certain direction (selecting the digital tubes to be lit through the bit selection interface), then inputs the pre-prepared encoding data to the segment selection pins, and maintains it for a certain period of time, and so on. Due to the persistence of vision effect of the human eye, the phenomenon we see is multiple displays at the same time. It is like flipping through an animated book when we were children. When we flipped through it quickly, we found that the small animals in the book started to run. At that time, I never tired of looking for various animation books. According to experience, when the frame rate is above 15fps, the animation is coherent, and the higher the frame rate, the smoother the animation. However, if the frame rate is too high, the information displayed on the digital tube will not be clearly visible. So an appropriate frame rate is the best. For our 6-digit digital tube, one scan (displaying 6 numbers) is one frame. We can observe the display effects of the digital tubes corresponding to different scanning frequencies and find the scanning method with better display effects. It was found through experiments that when each number is displayed for 10ms, the digital tube has obvious flickering phenomenon, and when it is changed to 5ms, the display is stable. Now that the principle is mastered, we can start writing code
1.5 Interface description
| Signal name | direction | FPGA pin number | illustrate |
|---|---|---|---|
| CLK_50M | enter | E1 | System clock, 50Mhz |
| KEY1 | enter | M1 | Independent button, press low level, used as reset |
| SMG_W0 | output | A2 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W1 | output | A3 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W2 | output | A4 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W3 | output | B5 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W4 | output | A5 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W5 | output | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection | |
| SMG_A | output | A9 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_B | output | K8 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_C | output | D8 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_D | output | A7 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_E | output | E7 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_F | output | B9 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_G | output | A10 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_DP | output | C8 | Digital tube segment selection control signal, low level lights up the segment |
Summary: Through the above explanation, the requirements can be interpreted as: when the first digital tube is lit, the bit selection is 6'h3e, and the code selected for the digital tube segment is 8'hf9; when the second digital tube is lit, , the bit selection is 6'h3d, and the code selected for the digital tube segment is 8'h25; when the third digital tube is lit, the bit selection is 6'h3b, and the code selected for the digital tube segment is 8'h0d; when the fourth digital tube is lit, When the fifth digital tube is lit, the bit selection is 6'h37, and the code selected for the digital tube segment is 8'h99; when the fifth digital tube is lit, the bit selection is 6'h2f, and the code selected for the digital tube segment is 8'h49; When the sixth digital tube is lit, the bit selection is 6'h1f, and the code selected for the digital tube segment is 8'h41;
2. Draw theoretical waveform diagram
3. Create a new QuartusII project
In order to make the project look tidy and facilitate project transplantation. We create 4 new folders, namely Project, Source, Sim, and Doc.
Project — project folder, which contains the QuartusII project
Source — source code folder, which contains the project source code (.v file or .vhd file)
Sim — simulation folder, which contains simulation-related files
Doc — stores related information , such as data manuals, requirements documents, etc.
4. Write code
///
//QQ:3181961725
//TEL/WX:13540738439
//工程师：Mr Wang
//模块介绍：数据管动态扫描，显示123456
module smg_drv(
input clk,
input rst_n,
output reg [5:0] smg_bit,
output reg [7:0] smg_seg
);
parameter refresh_time=50000;//一个时钟周期20ns，50000*20=1000000ns=1ms
reg [3:0] cnt;
reg [24:0] refresh_cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
refresh_cnt<=0;
else if(refresh_cnt==refresh_time-1)
refresh_cnt<=0;
else
refresh_cnt<=refresh_cnt+1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt<=4'hf;
else if(refresh_cnt==0&&cnt==5)
cnt<=0;
else if(refresh_cnt==0)
cnt<=cnt+1;
else;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
smg_bit<=6'h3f;
smg_seg<=8'h0;
end else case(cnt)
0:begin smg_bit<=6'h1f;smg_seg<=8'h9f; end
1:begin smg_bit<=6'h2f;smg_seg<=8'h25; end
2:begin smg_bit<=6'h37;smg_seg<=8'h0d; end
3:begin smg_bit<=6'h3b;smg_seg<=8'h99; end
4:begin smg_bit<=6'h3d;smg_seg<=8'h49; end
5:begin smg_bit<=6'h3e;smg_seg<=8'h41; end
default:;
endcase
end
endmodule
5. Write simulation test stimulus file
During simulation, our main concern is the input port. The input signals in this experiment are clk and rst_n, so we only assign values to these two signals to generate incentives. The simulation code is as follows:
`timescale 1ns/1ns
module smg_drv_tb;
reg clk ;
reg rst_n ;
initial
begin
clk = 0;
rst_n=0;
#1000
rst_n=1;
end
always #10 clk=~clk;
smg_drv Usmg_drv(
.clk (clk),
.rst_n (rst_n),
.smg_bit (),
.smg_seg ()
);
endmodule
6.Modelsim simulation
This routine is very simple and uses only one statement, so no simulation verification is required. But in order to demonstrate a complete development process to everyone, we also created a new simulation project for this experiment, starting from the simplest code to teach you how to write simulation stimulus files and how to use Modelsim software for simulation. Add the source code written in the third step and the simulation test stimulus file written in the fourth step to the Modelsim simulation project to simulate and observe the waveform.
There are generally two methods for Modelsim simulation:
-
Graphical interface simulation means that all operations are completed on the Modelsim software interface. The advantage of this method is that it is easy to learn and suitable for simple projects. The disadvantage is that the operation steps are cumbersome.
-
Batch simulation , this method requires writing corresponding script files before simulation. The advantage of this method is that the simulation can be completed with one click, saving time and effort. The disadvantage is that script files need to be written in the early stage. In order to quickly apply what everyone has learned to engineering practice, only the first experiment and the second experiment were simulated using a graphical interface, and all subsequent experiments were simulated using batch processing. In order to be closer to the engineering reality, we use batch processing simulation. The simulated waveform is shown in the figure below:
7. Compare waveforms
Compare the theoretical waveform diagram drawn in the second step with the waveform diagram simulated by Modelsim in the sixth step. The results are consistent, indicating that our logic design is correct. If the comparison results are found to be inconsistent, you need to find the reason for the inconsistency, and ultimately ensure that the comparison results are consistent.
By comparison, the theoretical waveform is consistent with the simulated waveform, indicating that the function meets the design requirements.
8. Compilation and synthesis
9. Bind pins
When the project is compiled successfully, pin assignment can be made (you need to refer to the schematic diagram of the development board). The development boards and modules in our store are marked with signal names on the PCB, and you can directly refer to the physical connection relationships when binding pins.
The pin mapping relationship is as follows:
10. Compile and synthesize again
11 Download SOF file
After successful compilation and synthesis again, the generated SOF file can be downloaded to the development board.
After the download is successful, the experimental phenomena on the development board can be observed. If the experimental phenomena are consistent with the design requirements, it means that there is no problem with our design, that is, You can proceed to the next step of solidifying the JIC file.
12 Generate and solidify JIC files
FPGA has a characteristic that the configuration information will be lost after power failure, so we need to store the configuration information in the configuration chip (FLASH). After the development board is powered on, the FPGA will read the configuration information in the configuration chip, so the development The board can still work normally after powering off and on again. To solidify the program to the configuration chip, you need to generate a JIC file first. The steps to convert SOF files into JIC files are as follows:
12.1 file–>Convert Programming File…
12.2 Select the JIC file and configure the chip model and FPGA model
Label 1 : Select the format of the generated file, we choose the JIC file
Label 2 : Select the model of the configuration chip, we choose EPCS16
Label 3 : Modify the name and storage path of the generated JIC file
Label 4 : Click the left mouse button on the Flash Loader
Label 5 : Select As for the FPGA model, our development board uses the EP4CE6F17C8 FPGA, so we should also choose this model, as shown in the figure below:
12.3 Select SOF file
Label 1 : Click the left mouse button on SOF Data
Label 2 : Add SOF file, select the SOF file generated by our project, as shown below:
12.3 Generate JIC file
At this point, the JIC file is generated and the curing operation can be performed.
12.4 Curing JIC files
After curing, the program will not be lost when the power is turned off!
Experimental phenomena
It matches the design requirements and the design is completed!