Passive buzzer driver experimental routine explanation
Based on many years of work experience, the FPGA design process has been summarized in a total of the above 12 steps, some of which can be omitted depending on the difficulty of the project. For example, for very simple projects, we can omit the steps in the dotted box, but our introductory course, no matter how simple it is, will be explained according to these 12 steps.
1. Interpretation of requirements
1.1 Requirements
Press KEY2 to activate the buzzer alarm, release KEY2 to turn off the alarm
1.2 Knowledge background
The buzzer is an electronic sounder with an integrated structure. It is widely used in alarms, electronic toys, automotive electronic equipment, telephones, timers and other electronic products because of its small size, light weight, low price and solid structure. As a sound-producing device. This chapter will introduce in detail how to use buttons to control the buzzer sound.
1 Introduction to buzzers
Buzzers can be divided into two types: electromagnetic buzzers and piezoelectric buzzers according to their structures. The electromagnetic buzzer consists of an oscillator, electromagnetic coil, magnet, vibrating diaphragm and shell. The piezoelectric buzzer is mainly composed of a multivibrator, a piezoelectric buzzer, an impedance matcher, a resonance box, and a shell. Piezoelectric buzzers use the piezoelectric effect of piezoelectric ceramics to drive the vibration of metal sheets to produce sound; while electromagnetic buzzers use the principle of electromagnetism to suck down the metal vibrating diaphragm when energized. Rebound by the elasticity of the diaphragm. Due to the different sounding principles of the two buzzers, the voltage type has a simple and durable structure but a single tone and poor timbre, so it is suitable for alarms and other equipment; while the electromagnetic type has good timbre, so it is mostly used in voice, music and other equipment.
Buzzers are divided into active buzzers and passive buzzers according to whether they have a signal source. The active buzzer is equipped with an integrated circuit inside and does not require an audio driver circuit. It only needs to be connected to a DC power supply to make a sound directly. The passive buzzer can only make sound with an external audio drive signal.
The active buzzer can only emit a fixed frequency sound and is not suitable for use as a music player. In order to make our development board more comprehensive, we choose a passive buzzer, so here is an introduction to the passive buzzer. Drive mode.
2. Passive buzzer driving principle
Passive buzzer is different from active buzzer. Because it does not have an oscillation source inside, it cannot be driven directly by DC signal like active buzzer. PWM is required here. A square wave can drive it to make sound.
How to make different sounds? It is mentioned above that a PWM square wave is required to drive it to produce sound, so here we only need to control the input PWM square wave. The sounds produced by inputting PWM square waves with different frequencies and duty cycles are different. The sounds emitted by square waves with different frequencies and duty cycles are different. The frequency has an impact on the tone, and the duty cycle has an impact on the volume. So we only need to generate PWM square waves of different frequencies and duty cycles to drive the passive buzzer to make the passive buzzer emit different tones.
The frequency of PWM : refers to the number of times the signal goes from high level to low level and back to high level within 1 second (one cycle); that is, how many cycles of PWM are there in one second. Unit: Hz
The relationship between PWM period and frequency:
T=1/f
period=1/frequency
50Hz = 20ms one period
If the frequency is 50Hz, that is to say, one cycle is 20ms, then there are 50 PWM cycles in one second.
Duty cycle : It is the ratio of high level time to the entire cycle time in a pulse cycle.
Unit: % (0%-100%)
Expression: 20%
In the above figure, the period is T.
T1 is the high level time
and T2 is the low level time.
Assume that the period T is 1s, then the frequency is 1Hz, the high level time is 0.5s, the low level time is 0.5s, the total duty cycle (T1/T) is 0.5 /1 =50%
1.3 Hardware design
1.4 Interface description
| Signal name | direction | FPGA pin number | illustrate |
|---|---|---|---|
| CLK50M | enter | B10 | Clock signal, 50MHZ |
| KEY1 | enter | E4 | When pressed, it is low level, and when released, it is high level, which is used as a reset signal. |
| KEY2 | enter | B3 | When pressed, it is low level, and when released, it is high level, which is used as a buzzer control signal. |
| BEEP | output | F14 | PWM square wave for driving passive buzzer |
Summary: Through the above description, the requirements can be interpreted as: press KEY2, the M13 pin outputs a PWM signal of a certain frequency, and the buzzer sounds; release the button, the M13 pin is set to high level, and the buzzer stops sounding
2. Draw theoretical waveform diagram
* Through the above picture, can you calculate the frequency of the square wave (beep)? Assume that the clock clk is 50Mhz (period 20ns) and a beep signal cycle has 2x (pwm_num+1) clk cycles (some students may ask, why is it pwm_num+1 cycles? That is because it is calculated from 0). Therefore, the period of beep is equal to 2x(pwm_num+1) 20 (unit ns), converted into seconds, it is equal to 2x(pwm_num+1)x20/1000/1000/1000, so the frequency is equal to 1/(2x(pwm_num +1)x20/ 1000/1000/1000) unit HZ. If pwm_num=1000, then the frequency is equal to 24975HZ.
3. New TD project
In order to make the project look tidy and facilitate project transplantation. We create 4 new folders, namely Project, Source, Sim, and Doc.
Project — the project folder, which contains the TD project
Source — the source code folder, which contains the project source code (.v file or .vhd file)
Sim — the simulation folder, which contains the simulation-related files
Doc — stores relevant information , such as data manuals, requirements documents, etc.
4. Write code
///
//QQ:3181961725
//TEL/WX:13540738439
//工程量：Mr Wang
//模块介绍：产生一定频率的方波（PWM波）驱动无源蜂鸣器
///
module alarm_ctrl(
input clk ,
input rst_n ,
input key ,
output beep
);
parameter pwm_num=20000;
reg [15:0] cnt=0;
reg beep_tmp;//PWM信号
assign beep=(key==0)?beep_tmp:1'b1;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt<=0;
else if(cnt==pwm_num)
cnt<=0;
else
cnt<=cnt+1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
beep_tmp<=0;
else if(cnt==0)
beep_tmp<=~beep_tmp;
else;
end
endmodule
5. Write simulation test stimulus file
Simulation test stimulus file (TB file)
`timescale 1ns/1ps
module alarm_ctrl_tb;
reg clk;
reg rst_n;
reg key;
initial
begin
clk=0;
key=1;//按键未按下
rst_n=0;//生成复位激励信号
#1000
rst_n=1;//生成复位激励信号
#1000000
key=0;
end
//生成时钟激励信号
always #10 clk<=~clk;
//例化被仿真模块
alarm_ctrl Ualarm_ctrl(
.clk (clk),
.rst_n (rst_n),
.key (key),
.beep ()
);
endmodule
6.Modelsim simulation
There are generally two methods for Modelsim simulation:
-
Graphical interface simulation means that all operations are completed on the Modelsim software interface. The advantage of this method is that it is easy to learn and suitable for simple projects. The disadvantage is that the operation steps are cumbersome.
-
Batch simulation , this method requires writing corresponding script files before simulation. The advantage of this method is that the simulation can be completed with one click, saving time and effort. The disadvantage is that script files need to be written in the early stage. The first two lectures use graphical interface simulation; in order to be closer to engineering reality, starting from the third lecture, we use batch processing simulation. For specific operation steps, please refer to our video tutorial.
The simulated waveform is shown below:
7. Compare waveforms
Compare the theoretical waveform diagram drawn in the second step with the waveform diagram simulated by Modelsim in the sixth step. The results are consistent, indicating that our logic design is correct. If the comparison results are found to be inconsistent, you need to find the reason for the inconsistency, and ultimately ensure that the comparison results are consistent. By comparison, the theoretical waveform is consistent with the simulated waveform, indicating that the function meets the design requirements.
8 Add .v file
9 Bind the pins and save the constraint file (.adc)
10 Compile and synthesize the BIT file
11. Download BIT file
After the download is successful, you can observe the experimental phenomena on the development board. If the experimental phenomena match the design requirements, it means that there is no problem with our design, and we can proceed to the next step of solidifying the configuration file.
12 solidification configuration file
FPGA has a characteristic that the configuration information will be lost after power failure, so we need to store the configuration information in the configuration chip (FLASH). After the development board is powered on, the FPGA will read the configuration information in the configuration chip, so the development The board can still work normally after powering off and on again.
After the curing is successful, power off the development board and then power it on again. It can be observed that the development board can still perform the functions just now.