Explanation of digital tube dynamic scanning display routine
Based on many years of work experience, the FPGA design process has been summarized in a total of the above 12 steps, some of which can be omitted depending on the difficulty of the project. For example, for very simple projects, we can omit the steps in the dotted box, but our introductory course, no matter how simple it is, will be explained according to these 12 steps.
1. Interpretation of requirements
1.1 Requirements
Stable display of 123456 on the six-digit digital tube
1.2 Knowledge background
The digital tube is an "8"-shaped device composed of multiple LED light-emitting diodes. According to different polarities, it is divided into common anode and common cathode. Our development board uses a common anode digital tube. The internal structure of the digital tube is as shown below:
As can be seen from the figure, the difference between common anode and common cathode. The common terminal of the common anode is connected to the positive terminal of the power supply, and the common terminal of the common cathode is connected to the ground. When choosing a common anode digital tube, we only need to set the corresponding abcdefgdq to a low level to light up the corresponding digital tube. On the contrary, the common cathode needs to connect abcdefgdq to the positive pole of the power supply to light up the corresponding digital tube. The schematic diagram of the digital tube is as follows:
The development board we chose uses a common anode digital tube. If we want to display 2, then we should light up the
A, B, G, E, and D LEDs. If you want to display 5, you can analyze by yourself which segments should be lit, so that we can get the codes from 0 to 9 of the common yang digital tube. In order to save everyone's time, I have sorted out the codes corresponding to the common Yang digital tube, as shown below, which can be called directly. The coding of the common cathode digital tube only requires bitwise inversion.
The development board common yang digital tube segment selection coding table is as follows:
1.3 Hardware design
The development board uses a PNP transistor. When a low level is input to the base of the transistor, the collector and emitter of the transistor are connected, and a voltage of 3.3V is applied to the bit selection pin of the digital tube. Then we need To light up the first digital tube, you need to input low level to SMG_W0, and assign values to the segment selection of the digital tube according to the digital tube coding table. Now that the principle is mastered, we can start writing code
1.4 Interface description
| Signal name | direction | FPGA pin number | illustrate |
|---|---|---|---|
| SMG_W0 | output | E12 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W1 | output | B15 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W2 | output | E15 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W3 | output | H11 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W4 | output | K16 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W5 | output | K14 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_A | output | F13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_B | output | B16 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_C | output | J16 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_D | output | J13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_E | output | G14 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_F | output | E13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_G | output | G12 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_DP | output | J14 | Digital tube segment selection control signal, low level lights up the segment |
Summary: Through the above explanation, the requirements can be interpreted as: when the first digital tube is lit, the bit selection is 6'h1f, and the code selected for the digital tube segment is 8'h9f; when the second digital tube is lit, , the bit selection is 6'h2f, and the code selected for the digital tube segment is 8'h25; when the third digital tube is lit, the bit selection is 6'h37, and the code selected for the digital tube segment is 8'h0d; when the fourth digital tube is lit, When the fifth digital tube is lit, the bit selection is 6'h3b, and the code selected for the digital tube segment is 8'h99; when the fifth digital tube is lit, the bit selection is 6'h3d, and the code selected for the digital tube segment is 8'h49; When the sixth digital tube is lit, the bit selection is 6'h3e, and the code selected for the digital tube segment is 8'h41;
2. Draw theoretical waveform diagram
3. New TD project
In order to make the project look tidy and facilitate project transplantation. We create 4 new folders, namely Project, Source, Sim, and Doc.
Project — the project folder, which contains the TD project
Source — the source code folder, which contains the project source code (.v file or .vhd file)
Sim — the simulation folder, which contains the simulation-related files
Doc — stores relevant information , such as data manuals, requirements documents, etc.
4. Write code
///
//QQ:3181961725
//TEL/WX:13540738439
//工程师：Mr Wang
//模块介绍：数据管动态扫描，显示123456
module smg_drv(
input clk ,
input rst_n ,
output reg [5:0] smg_bit ,
output reg [7:0] smg_seg
);
parameter refresh_time=50000;
reg [3:0] cnt;
reg [19:0] refresh_cnt;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
refresh_cnt<=0;
else if(refresh_cnt==refresh_time-1)
refresh_cnt<=0;
else
refresh_cnt<=refresh_cnt+1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt<=4'hf;
else if(refresh_cnt==0)begin
if(cnt==5)
cnt<=0;
else
cnt<=cnt+1;
end else;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
smg_bit<=0;
smg_seg<=0;
end else case(cnt)
0:begin smg_bit<=8'h3e; smg_seg<=8'h9f;end
1:begin smg_bit<=8'h3d; smg_seg<=8'h25;end
2:begin smg_bit<=8'h3b; smg_seg<=8'h0d;end
3:begin smg_bit<=8'h37; smg_seg<=8'h99;end
4:begin smg_bit<=8'h2f; smg_seg<=8'h49;end
5:begin smg_bit<=8'h1f; smg_seg<=8'h41;end
default:;
endcase
end
endmodule
5. Write simulation test stimulus file
`timescale 1ns/1ns
module smg_drv_tb;
reg clk ;
reg rst_n ;
initial
begin
clk = 0;
rst_n=0;
#1000
rst_n=1;
end
always #10 clk=~clk;
smg_drv Usmg_drv(
.clk (clk),
.rst_n (rst_n),
.smg_bit (),
.smg_seg ()
);
endmodule
6.Modelsim simulation
There are generally two methods for Modelsim simulation:
-
Graphical interface simulation means that all operations are completed on the Modelsim software interface. The advantage of this method is that it is easy to learn and suitable for simple projects. The disadvantage is that the operation steps are cumbersome.
-
Batch simulation , this method requires writing corresponding script files before simulation. The advantage of this method is that the simulation can be completed with one click, saving time and effort. The disadvantage is that script files need to be written in the early stage. The first two lectures used graphical interface simulation; in order to be closer to engineering reality, starting from this lecture, we will use batch processing simulation. For specific operation steps, please refer to our video tutorial.
The simulated waveform is shown below:
7. Compare waveforms
Compare the theoretical waveform diagram drawn in the second step with the waveform diagram simulated by Modelsim in the sixth step. The results are consistent, indicating that our logic design is correct. If the comparison results are found to be inconsistent, you need to find the reason for the inconsistency, and ultimately ensure that the comparison results are consistent. By comparison, the theoretical waveform is consistent with the simulated waveform, indicating that the function meets the design requirements.
8 Add .v file
9 Bind the pins and save the constraint file (.adc)
10 Compile and synthesize the BIT file
11. Download BIT file
After the download is successful, you can observe the experimental phenomena on the development board. If the experimental phenomena match the design requirements, it means that there is no problem with our design, and we can proceed to the next step of solidifying the configuration file.
12 solidification configuration file
FPGA has a characteristic that the configuration information will be lost after power failure, so we need to store the configuration information in the configuration chip (FLASH). After the development board is powered on, the FPGA will read the configuration information in the configuration chip, so the development The board can still work normally after powering off and on again.
After the curing is successful, power off the development board and then power it on again. It can be observed that the development board can still perform the functions just now.