LCD1602 display routine explanation
Based on many years of work experience, the FPGA design process has been summarized in a total of the above 12 steps, some of which can be omitted depending on the difficulty of the project. For example, for very simple projects, we can omit the steps in the dotted box, but our introductory course, no matter how simple it is, will be explained according to these 12 steps.
1. Interpretation of requirements
1.1 Requirements
The first line of the LCD screen displays "HELLO FPGA 1234!"
1.2 Knowledge background
1602 LCD is also called 1602 character LCD. It is a dot matrix LCD module specially used to display letters, numbers, symbols, etc. It consists of several 5X7 or 5X11 dot matrix character bits. Each dot matrix character bit can display one character. There is a dot interval between each bit and there is also an interval between each line, which plays the role of character spacing and line spacing. The role of spacing, because of this it cannot display graphics well (with custom CGRAM, the display effect is not good).
LCD1602 means that the displayed content is 16X2, that is, it can display two lines of 16-character LCD modules (displaying characters and numbers). Generally speaking, LCD1602 has 16 pins, and it is said that there are also 14 pins. Compared with the 16-pin one, it lacks the backlight power supply A (pin 15) and the ground wire K (pin 16). The actual object is shown in the picture below:
The pin definitions are as follows:
illustrate:
- VSS is connected to power ground.
- VDD is connected to +5V.
- VO is the bias signal of the liquid crystal display, which can be connected to a 10K potentiometer to adjust the display effect.
- RS is the command/data selection pin. When RS is low level, the command is selected; when RS is high level, data is selected.
- RW is the read/write selection pin. When RW is low level, write commands or data to LCD1602; when RW is high level, read status or data from LCD1602. If no reading operation is required, you can directly connect it to VSS.
- E, enable pin for command execution.
- D0—D7, parallel data input/output pins.
- A backlight positive electrode, connected to VDD.
- K backlight negative electrode, connected to VSS.
1.3 Hardware design
1.4 Interface description
| Signal name | direction | FPGA pin number | illustrate |
|---|---|---|---|
| CLK50M | enter | B10 | Clock signal, 50MHZ |
| LCD_RS | output | K12 | Command/data selection pin, when RS is low level, select command; when RS is high level, select data |
| LCD_RW | output | L16 | It is a read/write selection pin. When RW is low level, write commands or data to LCD1602; when RW is high level, read status or data from LCD1602 |
| LCD_CLK | output | K15 | Enable pin for command execution |
| LCD_DB0 | output | H15 | Parallel data input/output pin |
| LCD_DB1 | output | H13 | Parallel data input/output pin |
| LCD_DB2 | output | D14 | Parallel data input/output pin |
| LCD_DB3 | output | Q15 | Parallel data input/output pin |
| LCD_DB4 | output | F12 | Parallel data input/output pin |
| LCD_DB5 | output | A10 | Parallel data input/output pin |
| LCD_DB6 | output | G6 | Parallel data input/output pin |
| LCD_DB7 | output | G5 | Parallel data input/output pin |
2. Draw theoretical waveform diagram
3. New TD project
In order to make the project look tidy and facilitate project transplantation. We create 4 new folders, namely Project, Source, Sim, and Doc.
Project — the project folder, which contains the TD project
Source — the source code folder, which contains the project source code (.v file or .vhd file)
Sim — the simulation folder, which contains the simulation-related files
Doc — stores relevant information , such as data manuals, requirements documents, etc.
4. Write code
///
//QQ:3181961725
//TEL/WX:13540738439
//作者：Mr Wang
//模块介绍：LCD1602显示驱动
///
module lcd (
input clk ,//系统时钟输入50M
input rst_n ,//复位，低电平有效
output reg [7:0] dat ,//LCD的8位数据口
output reg rs ,//数据命令选择信号，高电平表示数据，低电平表示命令
output rw ,//读写标志，高电平表示读，低电平表示写，该程序我们只对液晶屏进行写操作
output en //LCD的控制脚
);
reg [15:0] counter ;
reg [ 5:0] current ;
reg clkr ;
reg e ;
//定义了LCD状态机需要的状态。
parameter set0 =6'd0;
parameter set1 =6'd1;
parameter set2 =6'd2;
parameter set3 =6'd3;
parameter set4 =6'd4;
parameter dat0 =6'd5;
parameter dat1 =6'd6;
parameter dat2 =6'd7;
parameter dat3 =6'd8;
parameter dat4 =6'd9;
parameter dat5 =6'd10;
parameter dat6 =6'd11;
parameter dat7 =6'd12;
parameter dat8 =6'd13;
parameter dat9 =6'd14;
parameter dat10=6'd15;
parameter dat11=6'd16;
parameter dat12=6'd17;
parameter dat13=6'd18;
parameter dat14=6'd19;
parameter dat15=6'd20;
parameter fini=6'hF1;
always @(posedge clk or negedge rst_n) //da de data_w1 zhong pinlv
begin
if(!rst_n)
begin
counter<=0;
clkr<=0;
end
else
begin
counter<=counter+1;
if(counter==16'h000f)
clkr<=~clkr;
else
;
end
end
always @(posedge clkr or negedge rst_n)
begin
if(!rst_n)
begin
current<=set0;
dat<=0;
rs<=0;
e<=1;
end
else
begin
case(current)
set0: begin e<=0;rs<=0; dat<=8'h38; current<=set1; end //*设置8位格式,2行,5*7*
set1: begin e<=0;rs<=0; dat<=8'h0C; current<=set2; end //*整体显示,关光标,不闪烁*/
set2: begin e<=0;rs<=0; dat<=8'h06; current<=set3; end //*设定输入方式,增量不移位*/
set3: begin e<=0;rs<=0; dat<=8'h01; current<=set4; end //*清除显示*/
set4: begin e<=0;rs<=0; dat<=8'h80; current<=dat0; end //设置显示第一行
dat0: begin e<=0;rs<=1; dat<="H"; current<=dat1; end
dat1: begin e<=0;rs<=1; dat<="E"; current<=dat2; end
dat2: begin e<=0;rs<=1; dat<="L"; current<=dat3; end
dat3: begin e<=0;rs<=1; dat<="L"; current<=dat4; end
dat4: begin e<=0;rs<=1; dat<="O"; current<=dat5; end
dat5: begin e<=0;rs<=1; dat<=" "; current<=dat6; end
dat6: begin e<=0;rs<=1; dat<="F"; current<=dat7; end
dat7: begin e<=0;rs<=1; dat<="P"; current<=dat8; end
dat8: begin e<=0;rs<=1; dat<="G"; current<=dat9; end
dat9: begin e<=0;rs<=1; dat<="A"; current<=dat10 ; end
dat10: begin e<=0;rs<=1; dat<="!"; current<=dat11; end
dat11: begin e<=0;rs<=1; dat<="1"; current<=dat12; end
dat12: begin e<=0;rs<=1; dat<="2"; current<=dat13; end
dat13: begin e<=0;rs<=1; dat<="3"; current<=dat14; end
dat14: begin e<=0;rs<=1; dat<="4"; current<=dat15; end
dat15: begin e<=0;rs<=1; dat<="6"; current<=fini; end
fini: begin e<=1;rs<=0; dat<=8'h00; end
default: current<=set0;
endcase
end
end
assign en=clkr|e;
assign rw=0;
endmodule
5. Write simulation test stimulus file
`timescale 1ns/1ns
module lcd1602_tb;
reg clk ;
reg rst_n ;
initial
begin
clk = 0;
rst_n=0;
#1000
rst_n=1;
end
always #10 clk=~clk;
lcd Ulcd(
.clk (clk),//系统时钟输入50M
.rst_n (rst_n),//复位，低电平有效
.dat (),//LCD的8位数据口
.rs (),//数据命令选择信号，高电平表示数据，低电平表示命令
.rw (),//读写标志，高电平表示读，低电平表示写，该程序我们只对液晶屏进行写操作
.en ()//LCD的控制脚
);
endmodule
6.Modelsim simulation
There are generally two methods for Modelsim simulation:
-
Graphical interface simulation means that all operations are completed on the Modelsim software interface. The advantage of this method is that it is easy to learn and suitable for simple projects. The disadvantage is that the operation steps are cumbersome.
-
Batch simulation , this method requires writing corresponding script files before simulation. The advantage of this method is that the simulation can be completed with one click, saving time and effort. The disadvantage is that script files need to be written in the early stage. The first two lectures use graphical interface simulation; in order to be closer to engineering reality, starting from the third lecture, we use batch processing simulation. For specific operation steps, please refer to our video tutorial.
The simulated waveform is shown below:
7. Compare waveforms
Compare the theoretical waveform diagram drawn in the second step with the waveform diagram simulated by Modelsim in the sixth step. The results are consistent, indicating that our logic design is correct. If the comparison results are found to be inconsistent, you need to find the reason for the inconsistency, and ultimately ensure that the comparison results are consistent. By comparison, the theoretical waveform is consistent with the simulated waveform, indicating that the function meets the design requirements.
8 Add .v file
9 Bind the pins and save the constraint file (.adc)
10 Compile and synthesize the BIT file
11. Download BIT file
After the download is successful, you can observe the experimental phenomena on the development board. If the experimental phenomena match the design requirements, it means that there is no problem with our design, and we can proceed to the next step of solidifying the configuration file.
12 solidification configuration file
FPGA has a characteristic that the configuration information will be lost after power failure, so we need to store the configuration information in the configuration chip (FLASH). After the development board is powered on, the FPGA will read the configuration information in the configuration chip, so the development The board can still work normally after powering off and on again.
After the curing is successful, power off the development board and then power it on again. It can be observed that the development board can still perform the functions just now.