Explanation of key debounce routine
Based on many years of work experience, the FPGA design process has been summarized in a total of the above 12 steps, some of which can be omitted depending on the difficulty of the project. For example, for very simple projects, we can omit the steps in the dotted box, but our introductory course, no matter how simple it is, will be explained according to these 12 steps.
1. Interpretation of requirements
1.1 Requirements
Each time you press the KEY1 button, the number displayed on the digital tube increases by 1, cycling from 0 to 9.
1.2 Knowledge background
Buttons are one of the most common electronic components and are widely used in electronic design. In FPGA experimental projects, we can use it as an external input for system reset signals or control signals; in daily life, remote controls, toys, calculators and other electronic products all use buttons. There are many types of buttons at present, the common ones include self-locking buttons, membrane buttons, etc. The mechanical buttons used on our development boards are also a type of buttons. Their characteristics are: small contact resistance, good feel, and a crisp "tick" sound when the button is pressed or popped up; however, due to its structure and principle, when the button is closed and broken, The moment it is turned on, there is a series of jitters.
In this experiment, we will design and implement a key debounce module based on the structure and principle of mechanical keys. Use the physical buttons on the development board as input signals, use the designed button debounce module to debounce the input button signals, output a button trigger signal that can be used normally, and then use this signal as a trigger signal for adding 1 to the counter. Each time the button is pressed, a trigger signal is generated, the counter increases by 1, and the number displayed on the digital tube also increases by 1.
The key switch we use is a mechanical elastic switch. When the mechanical contact is opened or closed, due to the elastic effect of the mechanical contact, a key switch will not be turned on immediately and stably when it is closed, nor will it be turned on when it is opened. Suddenly disconnected. Therefore, there will be a series of vibrations at the moment of closing and opening. To prevent this phenomenon, the measure taken is to eliminate the vibration of the button.
The length of the jitter time is determined by the mechanical characteristics of the key, generally 5ms~10ms. The length of the button's stable closing time is determined by the operator's button action, which is generally a few tenths to several seconds. Key jitter can cause a key to be misread multiple times. In order to ensure that the controller only processes a button closure once, the jitter of the button must be removed. The status of the button is read when the button is closed and stable, and the button must be released and stabilized before processing.
Debounce is to avoid the impact of severe level jitter when the button is pressed or lifted. There are two methods to debounce the keys, hardware or software. Here we only discuss software debouncing methods.
After detecting that the key is closed, a delay program is executed. According to the jitter time of 5ms~10ms, we generate a 20ms delay to allow the leading edge jitter to disappear and then detect the key state again. If the closed state level is still maintained, confirm For actual key presses.
1.3 Hardware design
Taking KEY1 as an example, when the button is not pressed, the network KEY1 is pulled up to 3.3V, which is a high level; when the button is pressed, the network KEY1 is directly connected to the ground, which is a low level.
1.4 Interface description
| Signal name | direction | FPGA pin number | illustrate |
|---|---|---|---|
| CLK50M | enter | B10 | Clock signal, 50MHZ |
| SMG_W0 | output | E12 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W1 | output | B15 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W2 | output | E15 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W3 | output | H11 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W4 | output | K16 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_W5 | output | K14 | Bit selection control signal, low level can turn on the transistor to power the digital tube bit selection |
| SMG_A | output | F13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_B | output | B16 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_C | output | J16 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_D | output | J13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_E | output | G14 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_F | output | E13 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_G | output | G12 | Digital tube segment selection control signal, low level lights up the segment |
| SMG_DP | output | J14 | Digital tube segment selection control signal, low level lights up the segment |
| KEY1 | output | E4 | Independent button, press low level |
Summary: Through the above explanation, the requirement can be interpreted as: press KEY1, the counter increases by 1, and the digital tube displays the counter value. In order to make the program structure clearer, we adopt a modular design method for this routine, including a key debounce module (key_xd), a digital tube display module (smg_drv), and a top-level module (key_xd_top).
2. Draw theoretical waveform diagram
3. New TD project
In order to make the project look tidy and facilitate project transplantation. We create 4 new folders, namely Project, Source, Sim, and Doc.
Project — the project folder, which contains the TD project
Source — the source code folder, which contains the project source code (.v file or .vhd file)
Sim — the simulation folder, which contains the simulation-related files
Doc — stores relevant information , such as data manuals, requirements documents, etc.
4. Write code
4.1 Key debounce module code
///
//QQ:3181961725
//TEL/WX:13540738439
//作者：Mr Wang
//模块介绍：实现按键消抖功能
///
module key_xd(
input rst_n ,//复位信号，低电平有效
input key_in ,//按键输入信号
input clk ,//50MHZ，一个时钟周期20ns
output reg key_out //输出信号，检测到有效按键时，输出一个高脉冲
);
parameter IDLE =4'd0;
parameter ST0 =4'd1;
parameter ST1 =4'd2;
parameter ST2 =4'd3;
parameter ST3 =4'd4;
parameter time_20ms=1000000;//20MS的时钟周期
reg [3:0] curr_st;
reg [20:0] wait_cnt;
reg key_in_ff1;
reg key_in_ff2;
//打两拍操作
always@(posedge clk)key_in_ff1<=key_in;
always@(posedge clk)key_in_ff2<=key_in_ff1;
//状态机
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
curr_st<=IDLE;
else case(curr_st)
IDLE:begin
if(key_in_ff2==0)
curr_st<=ST0;
else
;//curr_st<=IDLE;
end
ST0:begin
if(wait_cnt==time_20ms)
curr_st<=ST1;
else;
end
ST1:begin
if(key_in_ff2)
curr_st<=IDLE;
else
curr_st<=ST2;
end
ST2:curr_st<=ST3;
ST3:begin
if(key_in_ff2)
curr_st<=IDLE;
else
;
end
default:;
endcase
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
wait_cnt<=0;
else if(curr_st==ST0)
wait_cnt<=wait_cnt+1;
else
wait_cnt<=0;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
key_out<=0;
else if(curr_st==ST2)
key_out<=1;
else
key_out<=0;
end
endmodule
4.2 Digital tube display module code
///
//QQ:3181961725
//TEL/WX:13540738439
//作者：Mr Wang
//模块介绍：实现数码管显示
///
module smg_drv(
input clk ,//时钟信号，50MHZ
input rst_n ,//复位信号，低电平有效
input key_in ,//触发信号
output [7:0] smg_seg ,//数码管段选
output [5:0] smg_bit //数码管位选
);
reg [3:0] cnt;//0到9
reg [7:0] en_code;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt<=0;
else if(key_in&&cnt==9)
cnt<=0;
else if(key_in)
cnt<=cnt+1;
else ;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
en_code<=0;
else case(cnt)
0:en_code<=8'h03;//0的编码
1:en_code<=8'h9f;//1的编码
2:en_code<=8'h25;//2的编码
3:en_code<=8'h0d;//3的编码
4:en_code<=8'h99;//4的编码
5:en_code<=8'h49;//5的编码
6:en_code<=8'h41;//6的编码
7:en_code<=8'h1F;//7的编码
8:en_code<=8'h01;//8的编码
9:en_code<=8'h09;//9的编码
default:;
endcase
end
assign smg_seg=en_code;
assign smg_bit=6'h00;
endmodule
4.3 Top-level module code
///
//QQ:3181961725
//TEL/WX:13540738439
//作者：Mr Wang
//模块介绍：顶层模块，例化按键消抖模块和数码管显示模块
///
module key_xd_top(
input clk,
input rst_n,
input key_in,
output [7:0] smg_seg,
output [5:0] smg_bit
);
//例化按键消抖模块
key_xd key_xd(
.rst_n (rst_n),
.key_in (key_in),
.clk (clk),//50mHZ，一个时钟周期20ns
.key_out (key_out)
);
//例化数码管显示模块
smg_drv Usmg_drv(
.clk (clk),
.rst_n (rst_n),
.key_in (key_out),
.smg_seg (smg_seg),
.smg_bit (smg_bit)
);
endmodule
5. Write simulation test stimulus file
`timescale 1ns/1ns
module key_xd_top_tb;
reg clk ;
reg rst_n ;
reg key_in ;
reg [31:0] cnt=0;
parameter time_20ms=1000000;//20MS的时钟周期
initial
begin
clk = 0;
rst_n=0;
#1000
rst_n=1;
end
always #10 clk=~clk;
always@(posedge clk)cnt<=cnt+1;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
key_in<=1;
else if(cnt>time_20ms/2+time_20ms)//30ms~~
key_in<=$random;
else if(cnt<time_20ms/2)//0~10MS
key_in<=$random;
else if(cnt>time_20ms/2&&cnt<(time_20ms/2+time_20ms))//10ms~30ms
key_in<=0;
else;
end
key_xd_top Ukey_xd_top(
.clk (clk),
.rst_n (rst_n),
.key_in (key_in),
.smg_seg (),
.smg_bit ()
);
endmodule
6.Modelsim simulation
There are generally two methods for Modelsim simulation:
-
Graphical interface simulation means that all operations are completed on the Modelsim software interface. The advantage of this method is that it is easy to learn and suitable for simple projects. The disadvantage is that the operation steps are cumbersome.
-
Batch simulation , this method requires writing corresponding script files before simulation. The advantage of this method is that the simulation can be completed with one click, saving time and effort. The disadvantage is that script files need to be written in the early stage. The first two lectures used graphical interface simulation; in order to be closer to engineering reality, starting from this lecture, we will use batch processing simulation. For specific operation steps, please refer to our video tutorial.
The simulated waveform is shown below:
7. Compare waveforms
Compare the theoretical waveform diagram drawn in the second step with the waveform diagram simulated by Modelsim in the sixth step. The results are consistent, indicating that our logic design is correct. If the comparison results are found to be inconsistent, you need to find the reason for the inconsistency, and ultimately ensure that the comparison results are consistent. By comparison, the theoretical waveform is consistent with the simulated waveform, indicating that the function meets the design requirements.
8 Add .v file
9 Bind the pins and save the constraint file (.adc)
10 Compile and synthesize the BIT file
11. Download BIT file
After the download is successful, you can observe the experimental phenomena on the development board. If the experimental phenomena match the design requirements, it means that there is no problem with our design, and we can proceed to the next step of solidifying the configuration file.
12 solidification configuration file
FPGA has a characteristic that the configuration information will be lost after power failure, so we need to store the configuration information in the configuration chip (FLASH). After the development board is powered on, the FPGA will read the configuration information in the configuration chip, so the development The board can still work normally after powering off and on again.
After the curing is successful, power off the development board and then power it on again. It can be observed that the development board can still perform the functions just now.