STM32F4 in-depth learning [RCC]

Reset

System reset

System reset resets all registers, except for the reset flag and backup domain register in the clock control register CSR

Reset conditions:

1. External reset: NRST pin level is pulled low

2. WWDG reset: end of window watchdog count

3. IWDG reset: end of independent watchdog count

4. Software reset (core soft reset): Set the SYSRESEREQ (sys_reset_eq) bit in the application interrupt and reset control register (SCB_AIRCR) of the Cortex-M4 core to 1

   A core reset will occur in the following three situations :

   1. Power-on reset: The kernel automatically resets all components when the MCU is powered on
   2. System reset: only reset the processor and peripherals, not the kernel debug part (usually used for debugging)
   3. Processor reset: only reset the processor

   The duration of power-on reset and system reset depends on the MCU design. In some cases, the reset will last for several milliseconds to wait for the crystal oscillator clock to stabilize. After reset and before the processor runs the program, the Cortex-M processor will read the first two words from the memory, that is , the MSP Main Stack Pointer located before the interrupt vector table and the initial value of the reset vector . The reset vector is the starting address of the reset handle. After these two words are read by the processor, the processor will establish the main stack pointer MSP and the program counter PC with these two values.

   Reasons for establishing MSP in advance: After power-on, system errors may occur so that the processor calls NMI or hardware error-related service functions, and stack memory and MSP are needed to push some processor status information onto the stack to handle system error-related interrupts.

   Note: The SP initialization of Cortex-M4 is different from the initialization of the traditional ARM core. It must be initialized in software, and the interrupt vector table stores the address of the interrupt vector, because the M4 stack grows from top to bottom. The SP value of should be set to the first memory below the top of the stack, as shown in the following figure: The initial value of SP before the interrupt vector table is a pointer to the top of the stack

The following is the program related to system reset in the core_cm4.h file provided by arm, written in C embedded assembly code

__STATIC_INLINE void NVIC_SystemReset(void)
{
    
    
  __DSB();/* Ensure all outstanding memory accesses included
  			buffered write are completed before reset */
  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                            SCB_AIRCR_SYSRESETREQ_Msk    );/* Keep priority group unchanged */
  __DSB();/* Ensure completion of memory access */

  for(;;)/* wait until reset */
  {
    
    
    __NOP();
  }
}

5. Low power management reset

   Ways to trigger a low-power reset:

   1. Reset when entering standby: clear the nRST_STDBY bit in the user option byte. Once enabled, as long as the sequence to enter standby mode is successfully executed, the MCU will not enter standby, but will reset
   2. A reset is generated when entering the stop mode: clear the nRST_STOP bit in the user option byte. After being enabled, as long as the sequence to enter the stop mode is successfully executed, the MCU will not enter the stop mode, but will reset

Power reset

The addition to the backup register domain , all other registers are reset

The reset signal inside the MCU will be output on the NRST pin, and the pulse generator will ensure that the reset pulse of each internal reset source lasts at least 20us

condition:

1. Power-on/power-down/under-voltage reset
2. Exit standby mode reset

The reset circuit is as follows:

Backup domain reset

Backup domain reset will reset all RTC registers and RCC_BDCR register , but BKPSRAM will not be affected

The only way to reset BKPSRAM is to switch the FLASH protection level from 1 to 0 through the FLASH interface

Reset conditions:

1. Software reset: Set the BDRST bit in the RCC backup domain control register (RCC_BDCR) to 1
2. At $V_{DD}$And $V_{BAT}$After all power off, any one of them is powered on again

That is, the backup domain depends on $V_{BAT}$To maintain the operation in case of power failure, but if $V_{BAT}$Data cannot be saved in the backup domain when power is off

Clock control (RCC)

Clock source

From the system clock , the HSE clock, the master clock PLL HSI clock to drive one of the three

At the same time, MCU can be connected to **32kHz low-speed internal RC (LSI RC) to drive IWDG, and can also be used for automatic wake-up of RTC in shutdown/standby mode; it can also be connected to 32.768kHz low-speed external crystal oscillator (LSE crystal oscillator)** to drive RTC clock

Each clock source can be turned on or off independently, and the fewer clock sources that are turned on at the same time, the lower the power consumption

Clock tree

The internal clock of stm32f4 is quite complicated, with a multi-input-multi-output tree structure, which can be divided into the following main components

Bus clock

All internal buses can be clocked with multiple prescalers

AHB maximum frequency 168MHz

High-speed APB2 maximum frequency 84MHz

Low-speed APB1 maximum frequency 42MHz

Special peripheral clock

Peripherals	frequency	Clock source	Clock source frequency	Description
USB OTG FS	=48MHz	Specific PLL output	48MHz	PLL48CLK
RNG	<=48MHz	Specific PLL output	48MHz	PLL48CLK
SDIO	<=48MHz	Specific PLL output	48MHz	PLL48CLK
I2S clock	Data packet bit width*2*audio sampling frequency	Specific PLL output or external clock of I2S_CKIN pin		PLL I2S
USB OTG HS	=60MHz	External USB2.0 PHY	24-60MHz	USB HS ULPI
Ethernet	>=25MHz	Ethernet MAC clock provided by external PHY	25-50MHz	MACRXCLK, etc.
Ethernet		(Including TX, RX, RMII)		(See below)

The following figure shows the clock tree for special peripherals

System timer (SysTick) clock

Use 8-divided AHB clock (HCLK) or directly use AHB clock (HCLK)

Configurable in SysTick control and status register

Hardware timer clock

The timer clock frequency of stm32f42xxx and 43xxx is automatically set by hardware

According to the value of the TIIMPRE bit in the RCC_CFGR register, there are two cases

1. TIME = 0

   APB prescaler division factor is 1, set the timer clock TIMxCLK=PCLKx; otherwise, TIMxCLK=2*PCLKx

2. TIME = 1

   APB prescaler division factor is 1, 2 or 4, then set the timer clock TIMxCLK=HCLK; otherwise, TIMxCLK=4*PCLKx

Core free running clock

By the FCLK act as

Other peripheral clocks

All other peripheral clocks are provided by the system clock SYSCLK

Internal clock signal

HSE (High-speed Signal Extern)

Clock source: HSE external crystal or HSE external user clock

1. External source (HSE bypass) mode

An external clock signal with a duty cycle of approximately 50% must be provided to drive the OSC_IN pin

The signal can be one of square wave, sine wave or triangle wave

The OSC_OUT pin should be kept in a high impedance state

Set RCC_CR->HSEBYP=1 and RCC_CR->HSEON=1 to use this mode

2. External crystal (HSE crystal) mode

Hardware requirements: the resonator and load capacitor must be as close as possible to the oscillator pin to reduce output distortion and start-up stabilization time

The RCC_CR->HSERDY flag indicates whether the high-speed external oscillator is stable. The clock can be used only when the flag is 1.

Only RCC_CR->HSEON=1 can use HSE crystal oscillator, that is, RCC_CR->HSEON=1 and RCC_CR->HSERDY=1 can use this mode

In particular, you can enable interrupts in the RCC clock interrupt register RCC_CIR to enable interrupts in this mode

High-speed internal clock signal HSI (High-speed Signal Inner)

Clock source: internal 16MHz frequency RC oscillator

Can be used directly as system clock or as PLL input

Advantages: low cost, faster start-up speed Disadvantages: accuracy is not as good as HSE

ST will perform factory calibration on the device, and it can reach $T_A=25+$1% accuracy at$2$$7$$3$$K$ ; after reset, the factory calibration value will be loaded into the RCC_CR->HSICAL[7:0] bits, and the user can fine-tune the HSI frequency through the RCC_CR->HSITRIM[4:0] bits to adapt Various voltages or temperatures

The RCC_CR->HSIRDY flag bit is 1 indicating that the HSI RC is running stably. Only in this case can the HSI be used

Set RCC_CR->HSION=1 to open HSI RC

RCC_CR->HSION=1 and RCC_CR->HSIRDY=1 can use this mode

In special cases, the HSII signal can be used as a backup clock source to prevent HSE crystal oscillator failure

Phase Lock Loop Circuit PLL (Phase Lock Loop)

stm32f4xx has 2 PLLs

1. Main PLL (PLL)

   The clock signal is provided by HSE or HSI, with two different output clocks

   1. High-speed system clock output: up to 168MHz
   2. PLL48CLK output: up to 48MHz, used to provide USB OTG FS, RNG, SDIO clock

   Configured through the RCC_PLLCFGR register, there are 4 frequency division coefficient bits M, N, P, Q

2. Dedicated PLL (PLLI2S)

   Clock signal provided by HSE or HSI

   Used to generate a precise clock to achieve high-quality audio performance on the I2S interface

   Configure through the RCC_CFGR register, with enable/disable bit N and frequency division coefficient bit R
   

Note: After the PLL is enabled, the PLL configuration parameters cannot be changed. The PLL should be configured first, and then enabled

After entering the stop or standby mode, the two PLLs will be disabled by the hardware; if the HSE or the PLL provided by the HSE is used as the system clock, if the HSE fails, the two PLLs will also be disabled by the hardware

Low-speed external clock signal LSE (Low-speed Signal Extern)

Clock source: LSE external crystal or LSE external user clock

1. External source (LSE bypass) mode

An external clock signal with a duty cycle of about 50% and a maximum frequency of not more than 1MHz must be provided to drive the OSC32_IN pin

The signal can be one of square wave, sine wave or triangle wave

OSC32_OUT pin should be kept in a high impedance state

Set RCC_CR->LSEBYP=1 and RCC_CR->LSEON=1 to use this mode

2. External crystal (LSE crystal) mode

Hardware requirements: Use a 32.768kHz crystal oscillator with high accuracy and low power consumption. The resonator and load capacitor must be as close as possible to the oscillator pin to reduce output distortion and start-up stabilization time

The RCC_BDCR->LSERDY flag indicates whether the low-speed external oscillator is stable. The clock can be used only when the flag is 1.

Set RCC_CR->LSEON=1 to use LSE crystal oscillator, that is, RCC_CR->LSEON=1 and RCC_CR->LSERDY=1 can use this mode

In particular, you can enable interrupts in the RCC clock interrupt register RCC_CIR to enable interrupts in this mode

Low-speed internal clock signal LSI (Low-speed Signal Inner)

Can be used as a low-power clock source to keep running in shutdown and standby mode

Available for independent watchdog IWDG and automatic wake-up unit AWU

The clock frequency is around 32kHz

The RCC_CSR->LSIRDY flag indicates whether the low-speed internal oscillator is stable, and the clock can be used only when the flag is 1.

Set RCC_CR->LSION=1 to use LSE RC, that is, RCC_CR->LSION=1 and RCC_CR->LSIRDY=1 can use this mode

The interrupt can be enabled in the RCC clock interrupt register RCC_CIR to turn on the interrupt in this mode

System clock (SYSCLK)

System clock: the main clock inside the MCU, which provides the operating clock for the core processor

After the system is reset, the default system clock is HSI, and when HSI is used directly or through PLL as the system clock, the clock source cannot be stopped

Only when the target clock source is ready (the clock is stable after the start-up delay or the PLL is locked), can you switch from one clock source to another; if you select a clock source that is not yet ready, the switch will be performed when the clock source is ready. The ready status is indicated by the status flag bit in the RCC_CR register

Clock Security System (CSS)

The clock detector can be turned on by software. After activation, it will be enabled after the HSE oscillator start-up delay, and it will be turned off when the oscillator stops.

Responsible for monitoring the HSE clock signal

When HSE fails, this oscillator will be automatically disabled, CSS will send a clock failure time to the short-circuit input of TIM1 and TIM8, and generate a clock safety system interrupt CSSI to notify the software of the failure. CSSI directly communicates with the NMI of the M4 core (not allowed Mask interrupt) exception vector link

Note: If the HSE occasional failure, the CSS will generate an interrupt, NMI executed indefinitely, will need to NMI ISR CSS interrupt clear that the RCC_CIR-> CSSC = 1 in order to avoid such a situation

RTC/AWU clock

Once the RTCCLK clock source is selected, it can only be modified by resetting the power domain

Configure RCC_BDCR->RTCSEL[1:0] and RCC_CFGR->RTCPRE[4:0] to select the clock source

Clock sources that can be used for RTC:

1. HSE 1MHz: RTC status cannot be guaranteed after system power failure or internal voltage regulator shutdown
2. LSE: As long as $V_{BAT}$Just work to make RTC work
3. LSI: AWU status cannot be guaranteed after system power loss

Watchdog clock

The independent watchdog requires the LSI RC to be turned on and cannot be disabled. After the LSI is stable, it will be used for IWDG

Clock output function

1. MCO1

One of HSI, LSE, HSE, PLL clock can be output to MCO1 (PA8) through the prescaler

Select through RCC_CFGR->MCO1PRE[2:0] and MCO1[1:0]

2. MCO2

One of HSE, PLL, SYSCLK, PLLI2S clock can be output to MCO2 (PC9) through the prescaler

Select by RCC_CFGR->MCO2PRE[2:0] and MCO2[1:0]

Note: MCO output clock must not exceed the maximum IO speed (usually 100MHz)

The corresponding pin must be set to multiplexed mode to use the clock output function

Clock measurement

The frequency of all clock sources can be measured indirectly through the input capture of TIM5channel4 and TIM11channel1

TIM5channel4 measurement

TIM5 has an input capture multiplexer, which can select whether the input capture is triggered by IO or internal clock

Select by setting TIM5_OR->TI4_RMP[1:0] bits

The internal clock period can be measured with the help of the number of comparison signal counts between consecutive edges of the signal to be measured

$Bemeasuredchannelnumberperipheryof=\frac{Ratiothan\; thechannelnumber\; ofweeksof}{Ratiothan\; thechannelnumber\; ofthe\; number\; ofquantity}$

The greater the ratio of the frequency (period) of the comparison signal and the signal to be measured, the more accurate the result will be

TIM11channel1 measurement

TIM11 comes with an input multiplexer, you can select whether the input capture is triggered by IO or by internal clock

In addition, the HSE_RTC clock (HSE divided by a programmable prescaler) is connected to the channel1 input capture, which can be used to roughly indicate the frequency of the external crystal oscillator

Commonly used RCC library functions

function	Features
RCC_AHBPeriphClockCmd()	Enable/disable AHB peripheral clock
RCC_APB2PeriphClockCmd()	Enable/disable APB2 peripheral clock
RCC_APB1PeriphClockCmd()	Enable/disable APB1 peripheral clock
RCC_HSICmd()	Enable/disable HSI crystal oscillator
RCC_PLLConfig()	Set PLL clock source and frequency multiplication factor
RCC_PLLCmd()	Enable/disable PLL output
RCC_SYSCLKConfig()	Set the system clock SYSCLK
RCC_HCLKConfig()	Set AHB bus clock HCLK
RCC_PCLK1Config()	Set low-speed APB clock PCLK1
RCC_PCLK2Config()	Set high-speed APB clock PCLK2
RCC_USBCLKConfig()	Set the USB clock
RCC_ADCCLKConfig()	Set ADC clock
RCC_LSEConfig()	Set up LSE crystal oscillator
RCC_LSICmd()	Enable/disable LSE crystal oscillator
RCC_RTCCLKConfig()	Set RTC clock
RCC_RTCCLKCmd()	Enable/disable RTC clock
RCC_GetClocksFreq()	Returns the frequency of different on-chip clocks
RCC_BackupResetCmd()	Force/Release Backup Domain Reset
RCC_HSEConfig()	Set HSE crystal oscillator
RCC_GetSYSCLKSource()	Returns the clock source used as the system clock SYSCLK
RCC_ITConfig()	Enable/disable the specified RCC interrupt
RCC_GetITStatus()	Check whether the specified RCC interrupt occurs
RCC_ClearITPendingBit()	Clear RCC interrupt pending bit
RCC_GetFlagStatus()	Check whether the specified RCC flag is set