CCFC2012BC is developed based on the C*Core CPU core of NationalChip Technology's independent PowerPC architecture. It is a mid-to-high-end body and gateway control chip for automotive electronics. NXP (NXP) MPC5604BC, MPC5607B series and the replacement of ST's SPC560B50, SPC560B64 series of corresponding products
clock system
The system clock comes from three sources:
Other low-speed clock sources: 
Clock system diagram:
The peripheral set (1, 2 or 3) is obtained by frequency division or multiplication of the system clock, and the peripheral set (1, 2 or 3) is given to different peripherals respectively:
FMPLL clock configuration
CCFC22102B chooses FMPLL as the system clock, and the configuration of FMPLL clock frequency.
The above is to use FXOSC as the input clock source of FMPLL, and configure the FMPLL clock by setting the values of VCO, ODF, and NDIV. The FMPLL of CCFC22102B is 64mhz.
Register configuration information:
Code operation:
/*phi=(clkin*NDIV)/(IDF*ODF)=(16*32)/(2*4)=64MHz*/
CGM.FMPLL_CR.R = 0x05200100u;FMPLL configured as system clock
When CCFC22102B is running in RUN0, configure the following registers, configure FMPLL as the system clock, and the system clock is 64MHZ at this time;
union { /* RUN 0->4 Mode Configuration (+0x0030-0x003C) */
vuint32_t R;
struct {
vuint32_t :8;
vuint32_t PDO:1;
vuint32_t :2;
vuint32_t MVRON:1;
vuint32_t DFLAON:2;
vuint32_t CFLAON:2;
vuint32_t :9;
vuint32_t FMPLLON:1;
vuint32_t FXOSCON:1;
vuint32_t FIRCON:1;
vuint32_t SYSCLK:4;
} B;
} RUN[4];
/* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
ME.RUN[0].R = 0x001F0074u;The last 4 digits 4 are: corresponding to 0100:
Configuration of Peripheral Clocks
Configure in CGM_SC_DC0:
CGM.SC_DC[0].R = 0x80u; /* Enable system clock divider 0 */
CGM.SC_DC[1].R = 0x83u; /* Enable system clock divider 1 */
CGM.SC_DC[2].R = 0x80u; /* Enable system clock divider 2 */So peripheral set 0 is configured as 64mhz, peripheral set 1 is configured as 16mzh, and peripheral set 2 is configured as 64mhz.