0. Introduction
The method of transfer across clock domains, Cummings papers (see Appendix) speak in great detail, before he is seen in detail, in addition to his paper also read some other people talking about something on cross clock domains from the Internet, thinking that they have mastered the basic method across clock domains, interview, written completely false, but then, a few days ago to two faces AI chip companies in the clock domain crossing problems ignorance once again, of course, the whole interview process is suspended or beaten, had ignorant force.
The problem is: There is a counter APB IP interface, the CPU can write data, the control counter 10 or the like techniques to 5 arbitrary number, but the write data and the data receiving clock counter are asynchronous, and the desired maximum switching counter when the current count end can switch, such as a maximum value of 10, when counting to 6 to a new value 5, must be counted after 10, 5 to replace, should how to achieve this function, according to the particular interface APB about how the signal is given?
1. Methods
When he suggested that I use handshake, but I do not dare say, was thought to be resolved through handshake, but did not give him a satisfactory solution to sell, now that I think CPU can write data signal and a bit of valid packed into a data valid signal is the most significant bit, is to write the other data bits, the CPU write data onto the first PWDATA, let the next clock cycle valid effective, IP counter sampled data writing and saved, the current the end of the count, loading a new count value, the counter then send a response signal IP to the CPU via prdata.
2. Analysis
Beginning data onto the CPU PWDATA, the data will be the highest stable PWDATA pulled valid, the counter valid signal sampled IP register by two, there may occur metastability sampling, sample 0, but this does not affect the function , but will delay a sampling period only. Then the count value of the counter of the new preserved until the current loaded new count value after the end of the count. Then the answer to the CPU via prdata.
In this case it seems to be to achieve the desired function.
appendix
1. Synthesis and Scripting Techniques for Designing MultiAsynchronous Clock Designs
2. Simulation and Synthesis Techniques for Asynchronous FIFO Design
3. Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons