Core clock (system clock) = external clock (50M crystal frequency) / (pll_prdiv + 1) * (pll_vdiv + 24); MCG = PLL, core = MCG, bus = MCG / 2, FlexBus = MCG / 3, Flash clock = MCG / 8
https://blog.csdn.net/hcx25909/article/details/7164650
1. The system clock Freescale K60
As shown in FIG. Freescale K60 system clock, the clock source of the source can be found in a total of four devices:
① internal reference clock sources, including Fast IRC and slow IRC (IRC - Internal Reference Clock)
② external reference clock source, only EXTAL pin as a clock input, this can be achieved using an active crystal oscillator
③ external crystal resonator, the use of two EXTAL and XTAL input pins
④ 32K RTC external resonator, real-time clock for the clock input
Can be seen in the figures, to provide a clock signal as a system, the key is to ultimately generate an output MCGOUTCLK. MCGOUTCLK then after the division will be able to provide Core / system clocks, Bus clock, FlexBus clock and Flash clock. Produced MCGOUTCLK has three ways:
① directly from the external reference clock source Fast IRC, the clock source is integrated in a chip (including Slow IRC), 2M frequency
② provided by the FLL or PLL module
③ directly provided by an external clock, comprising an external reference clock source (an input pin), an external crystal resonator generated by the internal OSC logic XTAL_CLK RTC OSC logic and clock output.
In general, MCGOUTCLK FLL or PLL by generating a multiplier, Freescale official routine ultimately be generated by the PLL block. Can be seen in FIG PLL clock input module is the OSCCLK or RTC OSC logic. My board to the external reference clock source PLL clock multiplier to generate the final MCGOUTCLK by PLL. I.e. EXTAL -> PLL Modules -> MCGOUTCLK.
2. With regard to clock mode
Can be seen from the figure, the chip contains a total of up to eight different clock modes, plus Stop mode. FEI system directly into the default mode after RESET. FIG, F - FLL, P - PLL, E - Enable or the EXTAL (external clock), B - Bypass (bypass), I - Internal (internal reference clock), L - Low Power.
· FLL is enabled, the internal reference clock (FEI), the internal reference clock provides a clock FLL, FLL drive MCGOUT
· FLL is enabled, the external reference clock (FEE), external reference clock provides a clock FLL, FLL drive MCGOUT
· FLL bypassed, internal reference clock (FBI), FLL but although driven by an internal clock source in the operation MCGOUT
· FLL bypassed, external reference clock (FBE), FLL but although driven by an external clock source in the operation MCGOUT
· PLL bypass, the external reference clock (PBE), PLL operation while driving, but by an external reference clock source MCGOUT
· PLL enabled, the external reference clock (PEE), provide an external reference clock PLL clock, PLL drive MCGOUT
· BLPI FLL and PLL are disabled, the internal reference clock source drive MCGOUT
· BLPE FLL and PLL are disabled and an external reference clock source drive MCGOUT
Because the system after the reboot into the default mode of FEI, our goal is to jump PEE mode conversion, so to involve mode. FIG FEI by the PEE is not directly jump must be converted via other modes