Principles of Composition of Frequently Asked Questions in the Interview of Computer Entrance Examination (Part 2)
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In the review process, I carefully checked and sorted out most of the questions that may be asked during the postgraduate interview , and sorted out the answers in points . I can directly understand the recitation and add my own language polish ! I highly recommend printing to see it , efficiency higher!
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Some points are in the (Quick Awakening Memory Knowledge Framework), so they are not added!
There are a total of 8 articles in this series: Programming Languages | Data Structures | Operating Systems | Principles of Composition | Computer Networks | Databases | Software Engineering | Computer Professional English ( Not yet completed, so stay tuned, your Support and attention are my biggest motivation! )
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Chapter 4, Command System
Quickly arouse the memory knowledge framework :
15. The basic concept of instruction pipeline
Basic principles of pipeline:
Pipeline technology is a technology that significantly improves instruction execution speed and efficiency. The method is: after the instruction fetching is completed, the next instruction can be fetched without waiting for the execution of the instruction. If you further subdivide the interpretation process of an instruction, for example, it is divided into five sub-processes of fetching, decoding, fetching, executing, and writing back , and five sub-components are used to process these five sub-processes. After the first sub-process is processed, when the second sub-process is processed, the first sub-process of the second instruction is processed in the first sub-component. Over time, this overlapping operation can finally reach five sub-components Simultaneously operate the sub-process of five instructions.
Typical five-stage pipeline data path:
Features of the pipeline method:
Compared with the traditional serial execution method, the pipeline method has the following characteristics:
Decompose a task (an instruction or an operation) into several related sub-tasks, each sub-task is executed by a dedicated functional component, and rely on multiple functional components to work in parallel to shorten the execution time of the program.
There is a buffer register, or latch, behind each functional section of the pipeline. Its function is to save the execution result of the pipeline section and provide it for the next water section.
The time of each functional section in the pipeline should be as equal as possible, otherwise it will cause blockage and flow interruption.
Only when the same task is provided continuously can the efficiency of the pipeline be brought into play, so it is necessary to process continuous tasks in the pipeline. In the processor that uses the pipeline method, it is necessary to provide continuous tasks for the pipeline in many aspects such as software and hardware design.
The assembly line needs to have loading time and emptying time. Load time refers to the time from the first task entering the pipeline to the output pipeline. The emptying time refers to the time from the last task entering the pipeline to the output pipeline.
Factors affecting pipeline performance
1) Structural correlation is when multiple instructions compete for the same resource at the same time to form a conflict
Solution: (1) Pause for one clock cycle (2) Set up data memory and instruction memory separately
2) Data correlation occurs when instructions are overlapped and executed in the pipeline, when subsequent instructions need to use the execution result of the previous instruction.
Solution: (2) Pause for one clock cycle (2) Data bypass: input the ALU calculation result of the previous instruction directly to the next instruction
3) Control correlation is caused when the pipeline encounters branch instructions and other instructions that change the PC value.
Solutions: (1) Delay transfer technology. Swap the transfer instruction with the instruction or instructions before it that are not related to the transfer instruction, so that the successful transfer always occurs after the instruction that is followed is executed, so that the prefetched instruction is not invalidated.
(2) Transfer prediction technology.
16. Comparison between CISC and RISC (complex instruction set and reduced instruction set)?
17. Addressing mode in the knowledge framework of this chapter
Chapter 5, Central Processing Unit
Quickly arouse the memory knowledge framework: 
18. What is the function of CPU?
The central processing unit (CPU) is composed of an arithmetic unit and a controller. Among them, the function of the controller is to be responsible for coordinating and controlling each computer component to execute the instruction sequence of the program, including fetching instructions, analyzing instructions and executing instructions; the function of the calculator is to process the data. The specific functions of the CPU include:
- Command control. Complete the operations of fetching instructions, analyzing instructions and executing instructions, that is, sequential control of the program.
- Operation control. The function of an instruction is often realized by the combination of several operation signals. The CPU manages and generates the operation signal of each instruction fetched from the memory, and sends various operation signals to the corresponding parts, thereby controlling these parts to act according to the instructions.
- time control. Time control of various operations. Time control should provide the proper control signal for each instruction in chronological order.
- Data processing. Perform arithmetic and logical operations on the data.
- Interrupt processing. Handle abnormal situations and special requests that occur during computer operation.
19. The more pipelines, the higher the degree of parallelism. Does the more pipeline sections, the faster the instruction execution?
The reasons are as follows:
The extra overhead between pipeline buffers increases. Each pipeline segment has some extra overhead for functions such as transferring data between buffers, performing various preparations and sending, etc. These overheads increase the entire execution time of an instruction. When the logic between instructions is mutually dependent, the overhead is greater.
The control logic between the pipeline sections becomes more and more complicated. The control logic used for pipeline optimization and memory (or register) conflict handling will increase greatly with the increase of the pipeline stage, which may cause the logic used for control between pipeline stages to be more complicated than the control logic of the stage itself.
20. Several concepts related to instructions and data
When two consecutive instructions read the same register, there will be a Read After Read (RAR) correlation, which does not affect the pipeline.
When an instruction wants to read the register written by the previous instruction, it will generate a read after write (RAW) correlation, which is called data correlation or true correlation, which affects the pipeline. A pipeline that flows sequentially can only appear RAW related.
When the last instruction of a certain instruction wants to read / write the output register of that instruction, Write After Read (WAR) and Write After Write (WAW) will be related. In non-sequential pipelines, both RAW correlation, WAR correlation and WAW correlation may occur.
The most relevant instruction related to the pipeline is data related.
Chapter 6, Bus
Quickly arouse the memory knowledge framework:
21. What are the benefits of introducing a bus structure?
The introduction of the bus structure mainly has the following advantages: 1) Simplified the system structure, which is convenient for system design and manufacturing. 2) The number of wires is greatly reduced, which is convenient for wiring, reduces the volume, and improves the reliability of the system. 3) Convenient interface design, all devices connected to the bus use similar interfaces. 4) Facilitate the expansion, update and flexible configuration of the system, and Yiqian realizes the modularization of the system. 5) It is convenient for the software design of the equipment. The software of all interfaces operates on different interface addresses. 6) It is convenient for fault diagnosis and maintenance, and can also reduce costs.
22. Bus related concepts
1. According to the different transmission information, what types of system buses are divided? Is it unidirectional or bidirectional? 1) Divided into data bus, address bus and control bus. 2) Data bus: Data information is transmitted between the various functional components, bidirectional transmission; 3) Address bus: used to indicate the address of the main memory unit where the source or destination data is located on the data bus. Unidirectional: issued by the CPU 4) Control bus: used to send various control signals. The single line in the control bus is unidirectional, that is, it can only be sent from one component to another. In a group of control buses, there are inputs and outputs, so the control bus can also be regarded as bidirectional.
2. What are bus width, bus bandwidth, bus multiplexing, and number of signal lines? 1) Bus width: the number of data buses, generally a multiple of 8. It is an important indicator to measure the performance of computer systems; 2) Bus bandwidth: that is, the bus data transmission rate, the maximum number of bytes that can be transmitted on the bus per second. 3) Bus multiplexing: two signals are transmitted on one signal line in time-sharing. For example, time-division multiplexing of the data bus and address bus; 4) Number of signal lines: the sum of the number of lines of the address bus, data bus, and control bus.
Chapter VII, Input and Output System
Quickly arouse the memory knowledge framework:
23. What conditions should the CPU have to respond to interrupts?
1) The interrupt mask trigger set inside the CPU must be open.
2) When an interrupt request is provided externally, the interrupt request trigger must be in the "1" state to maintain the interrupt request signal.
3) Peripheral (interface) interrupt enable trigger must be "1" 'so that the peripheral interrupt request can be sent to the CPU.
When the above three conditions are met, the CPU responds to the interrupt in the last state cycle at the end of the current instruction.
24. What do the interrupt response priority and interrupt processing priority refer to?
The interrupt response priority is determined by the hardware queuing line or the query sequence of the interrupt query program and cannot be changed dynamically; and the interrupt processing priority can be changed by the interrupt mask word, reflecting whether the interrupt being processed is more recent The processing priority is low (the mask bit is "0", which is open to new interrupts). If it is, the interrupt being processed is aborted and the new interrupt is processed. After processing, the interrupt that was just aborted is returned to continue processing.
25. What is the relationship between the three concepts of vector interrupt, interrupt vector and vector address?
1) Interrupt vector: Each interrupt source has a corresponding processing program. This processing program is called an interrupt service program, and its entry address is called an interrupt vector. The interrupt service program entry addresses of all interrupts form a table, called the interrupt vector table; some machines form the jump instruction of the interrupt service program entry into a table, called the interrupt vector jump table.
2) Vector address: The memory address or index value of each entry in the interrupt vector table or interrupt vector jump table is called the vector address or interrupt type number.
3) Vectored interrupt: refers to a technique or method for identifying the source of an interrupt. The purpose of identifying the interrupt source is to find the address of the entry address of the interrupt service program corresponding to the interrupt source, that is, to obtain the vector address.
26. What is the difference between program interruption and calling subroutine?
The fundamental difference between the two is mainly reflected in the difference in service time and service target.
The time when the subroutine call process occurs is known and fixed, that is, the main program calls the subroutine process when the call instruction (CALL) in the main program is executed, and the location of the call instruction is known and fixed. The interruption time is generally random. When the CPU receives an interruption request from an interrupt source when executing a main program, the interruption process occurs, and the interruption application is generally generated by the hardware circuit, and the application time is random. It can also be said that the calling subroutine is arranged by the programmer in advance, and the execution of the interrupt service routine is randomly determined by the system working environment.
Subprograms serve the main program completely, and the two belong to the master-slave relationship. When the main program needs a subprogram, it calls the subprogram, and brings the result of the call back to the main program to continue execution. The interrupt service program and the main program are generally irrelevant, there is no question of who serves whom, and the two are in a parallel relationship.
The process of the main program calling the subroutine is completely a software process without special hardware circuit; and the interrupt processing system is a combined software / hardware system, which requires special hardware circuit to complete the interrupt processing process.
The nesting of subroutines can achieve several levels. The maximum number of nesting levels is limited by the stack size developed by the computer memory; the number of interrupt nesting levels is mainly determined by the interrupt priority level, and the general priority number is not very large.
27. I / O control method is available in the operating system, so I wo n’t repeat it here.