Verilog code
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 13:29:47 04/21/2018 // Design Name: // Module Name: lab14 // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module lab14( input E1, E2, E3, input A,B,C, output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 ); assign Y0 = ((E1 & !E2 & !E3) ==1'b1) ? !(!A & !B & !C) : 1'bz; assign Y1 = ((E1 & !E2 & !E3) ==1'b1) ? !(!A & !B & C) : 1'bz; assign Y2 = ((E1 & !E2 & !E3) ==1'b1) ? !(!A & B & !C) : 1'bz; assign Y3 = ((E1 & !E2 & !E3) ==1'b1) ? !(!A & B & C) : 1'bz; assign Y4 = ((E1 & !E2 & !E3) ==1'b1) ? !( A & !B & !C) : 1'bz; assign Y5 = ((E1 & !E2 & !E3) ==1'b1) ? !( A & !B & C) : 1'bz; assign Y6 = ((E1 & !E2 & !E3) ==1'b1) ? !( A & B & !C) : 1'bz; assign Y7 = ((E1 & !E2 & !E3) ==1'b1) ? !( A & B & C) : 1'bz; endmodule
Simulation code
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:56:28 04/21/2018
// Design Name: lab14
// Module Name: D:/Xilinx/lab14/testlab14.v
// Project Name: lab14
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lab14
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testlab14;
// Inputs
reg E1;
reg E2;
reg E3;
reg A;
reg B;
reg C;
// Outputs
wire Y0;
wire Y1;
wire Y2;
wire Y3;
wire Y4;
wire Y5;
wire Y6;
wire Y7;
// Instantiate the Unit Under Test (UUT)
lab14 uut (
.E1(E1),
.E2(E2),
.E3(E3),
.A(A),
.B(B),
.C(C),
.Y0(Y0),
.Y1(Y1),
.Y2(Y2),
.Y3(Y3),
.Y4(Y4),
.Y5(Y5),
.Y6(Y6),
.Y7(Y7)
);
initial begin
// Initialize Inputs
E1 = 0;
E2 = 0;
E3 = 0;
A = 0;
B = 0;
C = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
#5 E1 = 1;E2 = 0;E3 = 0;A = 0;B = 0;C = 0;
#5 E1 = 1;E2 = 0;E3 = 0;A = 0;B = 0;C = 1;
#5 E1 = 1;E2 = 0;E3 = 0;A = 0;B = 1;C = 0;
#5 E1 = 1;E2 = 0;E3 = 0;A = 0;B = 1;C = 1;
#5 E1 = 1;E2 = 0;E3 = 0;A = 1;B = 0;C = 0;
#5 E1 = 1;E2 = 0;E3 = 0;A = 1;B = 0;C = 1;
#5 E1 = 1;E2 = 0;E3 = 0;A = 1;B = 1;C = 0;
#5 E1 = 1; E2 = 0; E3 = 0; A = 1; B = 1; C = 1;
end
endmodule
simulation diagram