Principles of computer composition - I/O interface

• Program query method

  

• to interrupt
  • Interrupt sources: Various factors that make interrupt requests to the CPU
  • Direct memory access (DMA): There is a direct data path between I/O and main memory
  • Channel mode: has its own channel instructions but is controlled by the CPU

    

  • peripheral processor

    

• I/O interface composition and working principle

  

  • Interface functions: address identification and device selection, receiving and saving CPU I/O control commands, reflecting the working status of peripherals, signal conversion, data format, code system conversion, data error detection/correction, data transmission, interrupt
  • Composition: It consists of data buffer register DBR, status register, command register, port address decoding, control logic and interrupt logic
    • User perspective port: data port DBR, control port (command register), status port (status register)
    • Addressing:
      • Unified addressing I/O and memory are uniformly addressed
      • Independent addressing: I/O and memory have their own independent address spaces
    • Interface Type:
      • Transmission method: parallel, serial
      • Flexibility of Choice: Programmable, Non-Programmable
      • Versatility: general interface, special interface
      • Data transmission control method: interrupt, DMA
  • I/O command: 80x86 adopts I/O independent addressing: input command IN, output command OUT
    • Long format: IN AX/AL PORT, OUT PORT AX/AL
    • Short form: IN AX/AL DX, OUT DX AX/AL
    • The long format instruction has short interpretation time and fast I/O speed, and the short format can access more ports
  • Control method for data transmission
    • Program query I/O mode: CPU actively queries peripherals and works serially with I/O
• Interruption: Occurs randomly. Before the execution of the fixed-time instruction ends, the CPU sends an interrupt query signal to the interface to obtain the I/O interrupt request. Set INTR to 1, and the CPU executes the interrupt service program at the end of each instruction execution.
  • Only one interrupt source request can be serviced at any time
  • Interrupt system: hardware and software that implements interrupts
    • CPU: INTR that accepts the interrupt request signal, INTA that sends the interrupt response signal, interrupt status trigger INT, interrupt enable status flag EINT, open interrupt command STI that sets ENIT to 1, close interrupt command CLI that clears ENIT to 0, The interrupt return instruction IRET that bounces the program breakpoint back to the PC, etc.
    • Interrupt interface: interrupt request trigger INTR, interrupt mask trigger IM
    • Main memory: Interrupt service routines that handle different interrupt requests
  • process
    • interrupt request
    • interrupt arbitration
    • Interrupt response: If EINT is 1, the CPU scans the INTR pin at the end of each instruction execution. If there is a request, the CPU sets INT to 1 and enters the interrupt cycle to execute the interrupt implicit instruction
      • Interrupt implicit instruction: push the program breakpoint (current PC value) and the flag register FR into the stack; turn off the interrupt (clear EINT to 0), and send the first address of the interrupt handler to the PC
    • Interrupt service: protect the scene (interruption point protection, CPU register content protection), interrupt service, restore the scene
      • Form interrupt entry address: software query method, hardware vector method
      • can be sent to interrupt nesting

        

    • Interrupt return: execute the interrupt instruction STI and the interrupt return instruction IRET
  • Interrupt mask: The interrupt mask word is written into the interrupt mask register IMR, which can temporarily adjust the interrupt service sequence during operation (the highest priority is all 1)

    

  • Interrupt System of 8086 Microprocessor
    • hardware interrupt
      • NMI
      • maskable interrupt
    • Software interrupt (internal interrupt): division error, fixed-point addition overflow, breakpoint interrupt, single-step interrupt, interrupt instruction INTn
      • Except for single-step interrupts, internal interrupts cannot be disabled by software
    • Masking interrupts through the flags register allows the flag IF to be implemented. Processor scans INTR pin at end of each instruction execution, detects request signal checks IF (STI and CLI are active)
    • Interrupt cycle: send the interrupt response signal INTA, push the flag register FR onto the stack, clear IF and TF, push the register CS\IP onto the stack, find the entry address of the interrupt handler according to the interrupt type number, write into CS and IP
    • Interrupt instruction INTn: find the entry address of the interrupt handler according to the type number n
    • Interrupt return instruction IRET: 3 words are sequentially popped from the stack and sent to IP\CS\FR
    • Interrupt priority: software interrupt (divisor by 0, interrupt instruction, overflow interrupt), non-maskable interrupt, maskable interrupt, single-step interrupt

      

    • Interrupt features: macro parallel, micro none
• DMA: Direct Memory Access. direct realization, indirect realization

  

  • DMA controller DMAC composition: main memory address register, word counter, device address register, interrupt logic, control/status logic
  • Preprocessing -> Data Transfer -> Postprocessing

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  • Data transmission mode: single word, group, request
    • I/O sends a DMA request signal DREQ to DMAC, DMAC sends a bus occupation request to CPU, CPU decides whether to give up bus control, bus permission signal, DMA response signal DACK, data exchange with I/O, AR, WC increase by 1, DMAC cancels the HOLD signal to release the bus
  • CPU and DMAC share main memory/system bus
    • Stop the CPU from using the bus: the CPU is delayed

      

    • Cycle Stealing: Stealing cycle transfers when the CPU is not using the bus
      • When the CPU does not occupy the bus to access memory: the CPU immediately gives up the bus
      • CPU occupying bus memory access: give up the bus after the end of the current cycle
      • CPU request bus/imminent memory access: DMA priority is higher
    • Alternate use: split use within a cycle
  • example

    

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