1. As stm32f103VET6 concerned, there 4G address space; ram: 64KB; rom: 512KB; internal registers: Several; available from flash, ram, a system memory start
2. As S3C2440 is concerned, there are theoretically 4G address space; memory accessible to the controller 8 of the BANK size of 128MB; internal registers: Several; norflash and can be started from nandflash
Look at the code below:
@ ************************************************* ************************ @ File: head.S @ function: SDRAM, copy the program to the SDRAM, SDRAM and then proceed to jump @ * ************************************************** ********************** .equ MEM_CTL_BASE, 0x48000000 .equ SDRAM_BASE, 0x30000000 .text . , Ltd. Free Join _start _start: BL disable_watch_dog @ closed WATCHDOG, otherwise the CPU will continue to reboot the memory controller is provided bl memsetup @ bl copy_steppingstone_to_sdram @ copy the code to the SDRAM LDR PC, = on_sdram @ skip the SDRAM proceed on_sdram: LDR SP,= 0x34000000 @ stack disposed BL main halt_loop: B halt_loop disable_watch_dog: @ 0 can be written to the register WATCHDOG MOV R1, # 0x53000000 MOV R2, # 0x0 STR R2, [R1] MOV PC, LR @ returns copy_steppingstone_to_sdram: @ 4K, the Steppingstone all the data to be copied to the SDRAM @ Steppingstone start address 0x00000000, SDRAM starting address 0x30000000 MOV R1, # 0 LDR R2, = SDRAM_BASE MOV R3, # . 4 * 1024 . 1 : LDR R4, [R1], # . 4 @ Steppingstone 4 bytes read from the data, and to make the source address plus 4 STR R4, [R2], # 4 @ 4, copying the data into the SDRAM of this byte, destination address and so add 4 CMP R1, R3 @ determined whether or not: the source address is not equal to the address Steppingstone? bne 1b @ copied if not, continue mov pc, lr @ returns memsetup: @ disposed SDRAM memory controller to use other peripherals mov r1, a start address register 13 of the memory controller #MEM_CTL_BASE @ adrl r2, mem_cfg_val @ which 13 starting memory address values the add R3, R1, # 52 is @ 13 is * . 4 = 54 is . 1 : LDR R4, [r2], # . 4 @ read setting values, and so r2 added. 4 STR R4, [R1], # 4 @ This value is written into the register, and let r1 added. 4 CMP r1, R3 @ 13 determines whether setting all registers bne 1b @ written if not, continue mov pc, lr @ returns .align . 4 mem_cfg_val: @ storage controller 13 register set value . Long 0x22011110 @ BWSCON . Long 0x00000700 @ BANKCON0 . Long 0x00000700 @ BANKCON1 . Long 0x00000700 @ BANKCON2 . Long 0x00000700 @ BANKCON3 . Long 0x00000700 @ BANKCON4 . Long 0x00000700 @ BANKCON5 .long 0x00018005 @ BANKCON6 .long 0x00018005 @ BANKCON7 .long 0x008C07A3 @ REFRESH .long 0x000000B1 @ BANKSIZE .long 0x00000030 @ MRSRB6 .long 0x00000030 @ MRSRB7
sdram.bin : head.S leds.c arm-linux-gcc -c -o head.o head.S arm-linux-gcc -c -o leds.o leds.c arm-linux-ld -Ttext 0x30000000 head.o leds.o -o sdram_elf arm-linux-objcopy -O binary -S sdram_elf sdram.bin arm-linux-objdump -D -m arm sdram_elf > sdram.dis clean: rm -f sdram.dis sdram.bin sdram_elf *.o
In fact, it is the above phrase ldr pc, = on_sdram, a little bit difficult to understand, in fact, the makefile -Ttext 0x30000000 set the start position of the program code segments, so that bl disable_watch_dog first instruction address 0x30000000, the first instruction then executed in real ldr sdram SP, the address = 0x34000000 (i.e., the fifth instruction) is 0x30000010; bl and because the position-independent instructions can be executed in steppingstone, but is ldr execution address associated , it must be performed at the corresponding address, so that after the program is copied to sdram, can jump to perform from the steppingstone to sdram.