C ++ notes (Advanced 3): Makefile

1. Role

Make Makefile file tells how to compile and link into a program.

2. Makefile basic syntax and implementation

Examples
compile a single file HelloWorld.cpp

writeMakefile

HelloWorld : HelloWorld.cpp
  g++ HelloWorld.cpp -o HelloWorld
clean :
  rm HelloWorld

Compile

make

Clear

make clean

Constituting
Makefile mainly composed of a plurality of rules, each rule consists of three parts: a target ( target), dependent ( prerequiries) and command ( command).

Format
write Makefile in the following format

目标(target): 依赖(prerequiries)...
  命令(command)

Target (target) is usually the name of the file to be generated, is an example of the target executable or OBJ files. The name of a certain action may also be performed, such as a 'clean' (referred to as an operation target express only the imaginary object).
Is dependent on the input file is used to generate the target, a goal often dependent on several.
Make the action command is executed, a rule can contain several commands, each command per line.
note: Each command must be preceded by a Tab character, that character is a command line Tab. This is not careful easily go wrong.

Explanation

By default, make the first implementation of the first.
Use make way target name, perform the specified rules.

3. Makefile to compile multiple files

Examples

String.h

#ifndef _STRING_H_
#define _STRING_H_
#include <iostream>
using namespace std;
#include <string.h>
class String{
public:
    String(const char* cstr = NULL);
    String(const String& str);
    String& operator=(const String& str);
    ~String();
    char* c_str() const {
        return m_data;
    }
private:
    char* m_data;
};
ostream& operator<<(ostream& os, const String& str);
#endif // _STRING_H_

String.cpp

#include "String.h"
String::String(const char* cstr /*= NULL*/) {
    if (cstr) {
        m_data = new char[strlen(cstr) + 1];
        strcpy(m_data, cstr);
    }
    else {
        m_data = new char[1];
        *m_data = '\0';
    }
}
String::String(const String& str) {
    m_data = new char[strlen(str.m_data) + 1];
    strcpy(m_data, str.m_data);
}
String& String::operator=(const String& str) {
    //检测是否自我赋值
    if (this == &str)
        return *this;
    delete [] m_data;
    m_data = new char[strlen(str.m_data) + 1];
    strcpy(m_data, str.m_data);
    return *this;
}
String::~String() {
    delete[] m_data;
}
ostream& operator<<(ostream& os, const String& str) {
    os << str.c_str();
    return os;
}

StringTest.cpp

#include "String.h"
int main() {
    String s1;
    String s2("hello");
    String s3(s1);  //拷贝构造函数
    cout << s3 << endl;
    s3 = s2;    //拷贝赋值函数
    cout << s3 << endl;
    return 0;
}

makefile

StringTest:StringTest.o String.o
  g++ -o StringTest StringTest.o String.o
StringTest.o:StringTest.cpp String.h
  g++ -c StringTest.cpp
String.o:String.cpp String.h
  g++ -c String.cpp
clean :
  rm StringTest StringTest.o String.o

Description:

makePrior to implementation of the rules, check depend on whether there is or whether the latest. If it is not dependent on the implementation of the corresponding rules, create or update dependent

4. Variable simplified makefile

Each time a new document, the need to increase reliance in many parts of the makefile, easily lead to omissions. You can use variable can be simplified to avoid the possibility of such errors.

Variable definitions:变量 = 字符串
Variables:$(变量名)

Examples

makefile

OBJS = StringTest.o String.o

StringTest:$(OBJS)
  g++ -o StringTest $(OBJS)
StringTest.o:StringTest.cpp String.h
  g++ -c StringTest.cpp
String.o:String.cpp String.h
  g++ -c String.cpp
clean :
  rm StringTest $(OBJS)

In the makefile to use the name objects, OBJECTS, objs, OBJS, obj, or OBJvariables representing all OBJ files already agreed to be vulgar.

Explanation

A string variable is defined, in place of the multiple strings.

The command automatically derived

Compile .odocuments such very popular and commonly used, the rules are relatively simple

文件名.o:文件名.cpp 头文件
  g++ -c 文件名.cpp

makeProvides a simplified written, the rule can be automatically deduced

文件名.o:头文件

This simplified rule is called implicit rules, simplify rules become non-specific rules.

Examples

makefile

OBJS = StringTest.o String.o

StringTest:$(OBJS)
  g++ -o StringTest $(OBJS)
StringTest.o:String.h
String.o:String.h

clean :
  rm StringTest $(OBJS)

In general, the rules are grouped according to the target. Rules can also be grouped by their dependence. For example, examples String.oand StringTest.oare dependent String.h. Well, you can merge the two into a single rule.

OBJS = StringTest.o String.o

StringTest:$(OBJS)
 g++ -o StringTest $(OBJS)
StringTest.o String.o:String.h

clean :
 rm StringTest $(OBJS)

According to rely grouping rules can reduce the number of rules, in accordance with the rules of the target group more in line with our daily habits of mind.

6. hypothetical target

Expression of the target action is called imaginary target. The usual rules will generate or update a file with the same name as the target, but does not generate imaginary target file, just as a few names of commands special rules. For example, in the example clean, only perform cleanup actions. If, makefile sibling directory exists a file with the same name as the illusion of the target (for example: clean), it will result in a command will not be executed. So it is necessary to declare an imaginary target display target.

.PHONY 目标

Examples

makefile

OBJS = StringTest.o String.o

.PHONY: all clean

all:StringTest

StringTest:$(OBJS)
  g++ -o StringTest $(OBJS)
StringTest.o:String.h
String.o:String.h

clean :
  rm StringTest $(OBJS)

Common hypothetical target

No.	Hypothetical target	Features
1	`all`	Target goal of all this, the general objective is to compile all.
2	`clean`	Delete all files created by make.
3	`install`	Installation program has been compiled, the goal is to copy the executable file to the specified destination to go.
4	`print`	Lists the changed source files.
5	`tar`	Playing backup source tar package
6	`dist`	Create a compressed file, usually pressing the tar file into a Z file. Or gz file.

7. wildcards and variables

Compiled .ofiles can be written in a more general way, we have previously defined using a variable $(OBJS), automatically derive rules need to be generated.

makefile

OBJS = StringTest.o String.o

.PHONY: all clean

all:StringTest

StringTest:$(OBJS)
  g++ -o StringTest $^
$(OBJS):%.o:%.cpp
  $(CXX) -c $(CXXFLAGS) $< -o $@

.PHONY: clean

clean :
  rm StringTest $(OBJS)

Explanation

1. Wildcard
Wildcard is mainly used for matching file names, makefile used %as a wildcard. Extracting from the part of the string based on the wildcard matches the target name in the target format, and then assigned to each extracted character string according to the format-dependent dependence name. For example, use %.o:%.cpp.

2. automatic variable
automatic variables are in the rules of each execution based on the target and dependent variables produce new value. The following are common automatic variables.

No.	Automatic variables	meaning
1	`$<`	It represents a match-dependent
2	`$@`	It indicates the target
3	`$^`	All dependent

Here Insert Picture Description
3. predefined variables
predefined variables is a makefile variables already defined, the user can change the value of a variable in the makefile.

Program name variable

variable	program	Defaults
`CC`	C language compiler	`cc`
`CXX`	C ++ compiler	`g++`
`CPP`	With a standard C language preprocessor output	`$(CC) -E`

Variable program operating parameters
| variable | Program Parameters |
| - | - |
| CFLAGS| additional flags for the C compiler |
| CXXFLAGS| flag for additional C ++ compiler |