Makefile rules
foo.o:foo.c defs.h #module for twidding the frobs
cc -c -g foo.c
The first line in the present embodiment, the file "foo.o" rules need to rebuild the file, "foo.c" and "defs.h" rebuild the file "foo.h" required. We need to rebuild the rule file called the rule "target" (foo.h). The goal of rebuilding the documents needed to rule called "dependency." The second line rule "cc -c -g foo.c" is the "command" rule. It describes how to use the dependency file rules rebuilding target.
- Two ways to write the command rule :
A) and the target command: Description dependent on the same line. After the command file dependency list and a semicolon (;), and a separate list of dependencies;
B) in the target command: dependent described next line, as a separate command line. When the row as a separate command must now begin to [Tab] character. In the Makefile, after the first occurrence of a rule to all [Tab] character will be the beginning of the line as a command to deal with. - Makefile symbol "$" from special meaning (or a reference to a variable representing the function), requires the use of "$" rule in place, the need to write two consecutive ( "$$");
- A rule tells make two things: target under what circumstances has expired; if the target needs to be rebuilt, how to rebuild this goal. Whether the target date is determined by the dependencies of those rules of the use of space-separated. When the target file does not exist or the target file was last modified than relying on file in any of the night, the goal will be created or rebuilt.
- Command line execution rules with the proviso that one of both of the following :
A) the target file does not exist;
B) the target file exists, but dependent on the presence of a file rule in dependence last modification time is later than the last modification time; - The contents of the target file is determined by the dependent files, dependency files of any one change will result in the contents of the target file already exists expired.
- , A: such a rule BC, before the reconstructed object A, it is first required to complete the reconstruction of the B and C dependencies. B and C of the reconstruction process is the implementation of the rules Makefile to file B and C targets. Second, it identifies a dependency; rules if any object files depend on the new file is considered target rule has expired and the need to rebuild the target file. Normally, if any one is dependent file update rule, the target rule should also be updated accordingly.
- When updating dependence, you may not need to update the rules of the target. We call this kind is called "order-only" dependent. When writing rules, "order-only" dependent pipe symbol "|" began, as the target of a dependent file. The list of rules dependent on the pipe symbol "|" routine dependent on the left, to the right of the pipeline is "order-only" dependent. Written in the following format:
TARGETS: the NORMAL-the Prerequisites | the ORDER-ONLY-the Prerequisites
such a rule routinely rely file can be empty; also be a target for multiple additional dependent. Note: The rules depend on the file list if a file simultaneously appear in the list of regular and "order-only" list, then the file is treated as a regular dependent. - "Order-only" use-dependent Example:
LIBS = libtest.a
foo : foo.c | $(LIBS)
$(CC) $(CFLAGS) $< -o $@ $(LIBS)
make in the implementation of this rule, if the target file "foo" already exists When foo.c is modified target foo will be rebuilt, but when "libtest.a" is modified, the rule will not execute the command to rebuild target "foo". That is, the rule dependencies $ (LIBS) only if the target file does not exist, will participate in the implementation rules. When the target file exists This dependency will not participate in the implementation of the rules.
- Makefile can use wildcards when indicating the file name. Available wildcards are: "?", "*", And "[...]."
- In the case of the use of wildcards Makefile:
A) may be used in certain rules, dependence, when reading the make Makefile automatically subjected to matching processing;
B) may be present in the command rule, the process is a wildcard in the wild shell finished executing commands; - If the rule contains a file name wildcard characters ( "*", "." Character, etc.), using a backslash escape processing file names when using wildcard characters such files. For example "foo * bar", it expressed in the Makefile file "foo * bar
- Tilde "~" beginning of the file name has a special meaning. It is used alone or followed by a slash (~ /), representing the current user's home directory (in the shell can command "echo ( )" to view). For example, "~ / bin" on behalf of "/ home / username / bin / " ( current bin directory under the user's home directory). After a word with a wavy line (~ word), represented by the "word" host specified user directory. E.g. "~ john / bin" directory under the bin is to represent the home directory for the user john.
print: *.c
lpr -p $?
touch print
The above rules target an empty target file "print". (There is a current directory a file "print", but we do not care about its actual content, the role of this file only records the last time this rule to perform automatic loop variable "$?" Here means to be changed dependent on the file list all the files.
- Require variable "objects" on behalf of all .o files listed expressed the need to use the function "wildcard"
objects = $(wildcar *.o)
- To use the function "wildcard", its usage is: $ (wildcard PATTERN ...). In the Makefile, which are expanded using space-separated list is already exist, all files that match this pattern. If there are no files that meet this mode, the function ignores character mode and return empty.
- "$ (Wildcard * .c)" to get all the .c files in the working directory listing
- Use "
$(patsubst %.c,%.o,$(wildcard *.c))," first use "wildcard" function gets a list of .c files in the working directory; after the replacement list of all suffixes .c file name is .o. So that we can get .o be generated in the current directory
vpath PATTERN DIRECTORIES
"PATTERN" file to specify a search directory "DIRECTORIES" for all in line mode. Multiple directories with a space or a colon (:) to separate. Similar to the previous section of "VPATH" variable.
vpath PATTERN
Set search path for files that match pattern "PATTERN" before removal.
twenty one.
vpath
Clear all search path has been set.
22. vpath use the "PATTERN" mode need to include the characters "%." "%" Means matches one or more characters, e.g., "%. H" to represent all ".h" end of the file. "DIRECTORIES" specifies the type of file directories. When the list of dependencies rule in the file can not be found in the current directory, make the program will be followed in the directory "DIRECTORIES" described finding the file.
vpath %.h ../headers
The implication: .h file Makefile that appear; if you can not find in the current directory, then to the next "... / headers" to find.
- make while parsing the implementation of the rules Makefile file to the file path to save or discard is based on the algorithm is as follows :
A) If the rules of the target file does not exist in the directory where the makefile is located, then perform a directory search;
b) If the directory search is successful, the goal of this rule exists in the specified directory. Then searched was the full path name is stored as a temporary target file;
C) For all dependent files processing rule using the same method;
D) dependent on the completion of the processing of the third step, make the program can decide rules whether the target needs to be rebuilt, follow-up treatment when two situations are as follows:
the target does not need to re-establish the rule: it is obtained by the full catalog search elements all depend on the file path name is valid, equally, the full path name of the target file rules equally effective .
Target rules need to be rebuilt: So the full path name of the target file's directory search elements obtained by the invalid rule in the target file will be rebuilt in the working directory. - Makefile pseudo-objective: it does not represent a real file name, you can specify the target when you run make in order to perform their defined rules, sometimes also called a pseudo-target label.
- The goal is declared as a pseudo-target approach is to rely on it as a special target of .PHONY:
.PHONY : clean
- Another pseudo target used in the case of parallel execution and make recursion.
