[Linux] Brief introduction of Makefile

Table of contents

Foreword:

In the process of learning, it is enough to recognize the role of Makefile, understand its basic grammar and rules , understand and be able to use general Makefile to reduce the workload in actual projects.

(1) When using the gcc command to compile multiple .c files, take the following as an example, it needs to compile ac and bc in sequence, if the files in it are modified, it has to recompile all the files again, this is unnecessary.

(2) The above method is very inconvenient when dealing with large programs. When we modify the source file or header file, recompile the involved files, and then regenerate the application --- this is a more efficient compilation method.

(3) Using the above method, the make command is often used to compile programs in Linux, and the actions performed by the make command depend on the MakeFile file.

(4) The basic principle of Makefile: By comparing the modification time of the target file and the dependent file, it is judged whether it has been modified, and the corresponding action is executed when the dependent file is newer.

(5) The role of the existing general Makefile:

①Support multiple directories, multi-layer directories, and multiple files
②Support to set compilation options for all files
③Support to set compilation options for a certain directory
④Support to set compilation options separately for a file

1. Makefile rules

When we execute the make command, we will look for the Makefile in the current directory, and perform operations according to its instructions to generate the first target.

A simple Makefile rule looks like this:

target (target) ... : dependencies (prerequiries) ...

<tab> Command (command)

If the "dependency file" is newer than the "target file" or the target file does not exist, execute the "command" to regenerate the "target file".

Specific examples are as follows:

When we modify the ac file, recompile ac and relink to generate the corresponding program.

Second, the function syntax of Makefile

(1) wildcard pattern

Wildcard (pattern): streamline similar rules

$@: Indicates the target $<: Indicates the first dependent file $^: Indicates all dependent files

test: a.o b.o c.o
gcc -o test $^

%.o : %.c
gcc -c -o $@ $<

(2) delete clean

Used to delete target files.

clean:
rm *.o test

.PHONY: clean

(3) Immediate variable, delayed variable

A = xxx // Delay variable, it will be determined when it is used

B ?= xxx // Delay variable, the assignment is only successful when it is defined for the first time; if it has been defined, this assignment is invalid

C := xxx // Immediate variable, determined at the time of definition

D += yyy // If D was a delayed variable before, it is still a delayed variable now;

The above variables, do a small test.

According to the above description, the corresponding output results of A, B, and C are as follows:

(4) Common functions of Makefile

//Assign each element in the list to var, and then change var to the form described by text

$( foreach var,list,text)

//Whether the files listed in pattern exist, list all existing files

$( wildcard pattern)

/ / Take out the value that conforms to (does not conform to) the pattern format in the text

$( filter pattern...,text)

$( filter-out pattern...,text)

//Find the words in the text that match the pattern format, and replace them with replacement

$( patsubst pattern,replacement,text)

The above function makes a small test application.

The corresponding result: