2.1 Built-in data types
Generally, in Verilog, we have two common data types: variables and nets. They each have four states: 0, 1, Z, and X. The most common applications are reg and wire.
variable
Unsigned number: reg
32-bit signed number: integer
64-bit unsigned number or floating-point number: time
Several variables can be stored together in a fixed-width array. All storage is static, meaning that all variables are alive throughout the simulation.
Wire net
wire
line network is generally employed to connect different parts of the design. It is usually the port that connects the design module.
2.1.1 logic (logic) type
Compared to the usual Verilog reg type, the logic type has been improved on the basis of it, so that it can not only be used as a variable, but alsoDriven by continuous assignment, gate unit and module. Any data that uses wire mesh type can use logic.logic cannot have multiple structural driversWhen defining a bidirectional bus, you can only use wire instead of logic.
2.1.2 Two-state data types
Compared to four-state (0, 1, X, Z) data types, SystemVerilog introduces two-state (0, 1) data types, which helps improve the performance of the simulator and reduce memory Usage.
Unsigned single-bit data type bit, signed data types are byte, shortint, int, longint.
Example 2.2 Signed data type
bit b; //双状态，单比特，无符号
bit [31:0] b32; //双状态，32比特无符号整数
int unsigned ui; //双状态，32比特无符号整数
int i; //双状态，32位有符号整数
byte b8; //双状态，8比特有符号整数，取值范围为-128~127
shortint s; //双状态，16比特有符号整数
longint l; //双状态，64比特有符号整数
integer i4; //四状态，32比特有符号整数
time t; //四状态，64比特无符号整数
real r; //双状态，双精度浮点数
2.2 Fixed-width array
2.2.1 Declaration and initialization of fixed-width array
All arrays are indexed with 0 as the starting point, So SystemVerilog allows a convenient way to declare only the width of the array.
Example 2.4 Declaration of a fixed-width array
int lo_hi [15:0]; //16个整数[0]...[15]
int c_style [16]; //16个整数[0]...[15]
Create a multi-dimensional fixed-width array by specifying dimensions after the variable name.
Example 2.5 Declaring and using a multi-dimensional array with 8 rows and 4 columns
int array2 [0:7] [0:3]; //完整的声明
int array3 [8][4]; //紧凑的声明
int array2 [7][3]=1; //设置最后一个元素为1
In SystemVerilog, the emulator uses 32-bit word boundaries when storing data elements, so byte, shortint, and int are placed in one word, and longint is placed in two words.
2.2.2 Constant array
A single quote and parentheses to initialize the arrayNote that the single quotes here are different from the single quotes in the compiler guidelines or macro definitions.
Example 2.7 Initializing an array
int ascend [4]='{0,1,2,3}; //对4个元素进行初始化
int descend [5];
descend='{4,3,2,1,0}; //对5个元素进行初始化
descend[0:2]='{5,6,7}; //对前三个元素赋值
ascend=‘’{4{8}}； //四个值全部为8
descend ='{9,8,default:1}; //{9,8,1,1,1}
2.2.3 Basic operations
of arrays, the most common way for and foreach to operate on arrays isUse for or foreach loop. The $ size function will automatically return the width of the array. Foreach loop only need to specify the name of the array and give the index in the square brackets behind it, SystemVerilog will automatically traverse the elements in the array.
Example 2.8 Using for and foreach loops in array operations
module test_enum();
initial begin
bit[31:0] src[5],dst[5];
int i,j; //无需对i，j进行类型定义
for(int i=0;i< $size(src);i++)
begin
src[i]=i;
$display("src[%0d]=%0d",i,src[i]);
end
foreach(dst[j])
begin
dst[j]=src[j]*2; //dst的值是src的两倍
$display("dst[%0d]=%0d",j,dst[j]);
end
endmodule
The subscript of the square brackets of the foreach loop of the multi-dimensional array is not [i] [j], but [i, j].
Example 2.9 Initializing and traversing a multidimensional array
module test_enum();
int md[2][3]='{'{0,1,2},'{3,4,5}}; //对多维数组的赋初始值是在initial之外
initial begin
$display("Initial value:");
// int i,j; //并不需要对i,j进行类型定义
foreach(md[i,j]) //这是正确的语法格式
$display("md[%0d][%0d]=%0d",i,j,md[i][j]);
$display("new value:");
//对最后三个元素重复赋值5
md='{'{9,8，7}，'{3{32'd5}}}；
foreach(md[i,j]) //这是正确的语法格式
$display("md[%0d][%0d]=%0d",i,j,md[i][j]);
end
endmodule
Example 2.11 Printing a multidimensional array
module test_enum();
initial begin
byte twoD[4][6];
foreach(two[i,j])
twoD[i][j]=i*10+j;
foreach(twoD[i]) //遍历第一个维度
begin
$write("%0d:",i);
foreach(two[,j]) //遍历第二个维度
$write("%3d",two[i][j]); //利用位宽来表示空格
$display;
end
end
endmodule
2.2.4 Basic array operations-copy and compare
Example 2.13 Array copy and compare operations
module test_enum();
bit[31:0] src[5]='{0,1,2,3,4},
dst[5]='{5,4,3,2,1}; //赋初始值放在外面
initial
begin
//两个数组的聚合比较
if(src = = dst)
$display("src = = dst");
else
$display("src!=dst");
dst=src; //将src赋给dst
src[0]=5; //将src的第一个元素赋值为5
$display("src %s dst",(src== dst)? "= = ":"!="); //以这种方式来比较，所有元素的值是否相等
$display("src[1:4] %s dst[1:4]", //使用数组片段对第1-4个元素进行比较
(src[1:4] = = dst[1:4])? "==":"!=");
end
endmodule
2.2.5 Several ways of expressing arrays
1) Simultaneous use of array subscripts and bit subscripts
Example 2.14 Print out the first element of the array (binary 101), its least significant digit (1), and the immediately higher two digits ( Binary 10).
initial begin
bit [31:0] src[5]='{5{5}};
$displayb (src[0],, //'b101或'd5
src[0][0],, //'b1
src[0][2:1]); //'b10
end
2) Merge array
When declaring a merged array, the merged bits and array size must be indicated before the variable name as part of the data type. The format defined by the array size must be [msb: lsb], not [size].
An example
bit [3:0] [7:0] bytes; //四个字节合并的数组，使用单独的32比特的字来存放。
bytes=32'hCafe_Data;
$display (bytes,, //显示所有的32比特
bytes[3],, //最高位字节“CA”
bytes[3][7]); //最高字节的最高比特位“1”
bit [3:0][7:0] barray[3]; //合并3*32比特
barray[2]； //32比特的数据
barray[2][3]； //8比特的数据
barray[2][3][7]； //单比特的数据
2.3 Dynamic arrays
We know that the Verilog array types are all fixed-width arrays whose width is determined at compile time. But if we don't know the width of the array in advance, how should we allocate the width of the array? Now let's introduce the dynamic array.
Dynamic arrays use the empty subscript [] when they are declared. The array is empty at the beginning. You must use the new [] operator to allocate space and pass the array width in square brackets..
Example 2.17 using a dynamic array
module test_enum();
int dyn[],d2[]; //声明动态数组
initial
begin
dyn=new[5]; //dyn的宽度为5，分配5个元素
foreach(dyn[j])
dyn[j]=j; //对元素进行初始化
d2=dyn; //复制动态数组
d2[0]=5; //修改复制值
$display("%d %d",dyn[0],d2[0]); //显示数值0,5
dyn=new[20](dyn); //给dyn分配20个整数值并将前五个值进行复制
$display("%d %d",dyn[3],dyn[19]); //3,0
dyn=new[100]; //分配100个整数值给dyn，旧值不复存在
dyn.delete(); //删除所有元素
end
endmodule
2.4 Queue
SystemVerilog introduces a new data type queue. Adding or deleting elements anywhere in a queue, the performance loss of such operations is much smaller than dynamic arrays, because dynamic arrays need to allocate new arrays and copy all elements.
The declaration of the queue is a subscript [$] with a dollar sign, and the number of queue elements is from 0 to $. Note that the constant of the queue (literal) only has curly brackets and no single quotes at the beginning of the array constant。
module test_enum();
int j=1,
q2[$]={3,4}, //队列的常量不需要使用单引号'
q[$]={0,2,5}; //{0，2，5}
initial
begin
j=q2[$]; //j=4
j=q2[0]; //j=3
q.insert(1,1); //在第1位插入1{0,1,2,5}
q.insert(2,3); //在第2位插入3{0,1,3,2,5}
q.delete(1); //删除第一位{0,3,2,5}
//下面的操作执行速度很快
q.push_front(6); //最前面插入6{6,0,3,2,5}
j=q.pop_back; //j=5 {6,0,3,2}
q.push_back(8); //在最后插入8{6,0,3,2,8}
j=q.pop_front; //j=6{0,3,2,8}
foreach(q[i])
$display("%0d",q[i]); //打印整个队列
q.delete(); //等价于命令q={};删除整个队列
end
endmodule
Note: Putting $ on the left side of a range expression, then $ will represent the minimum value [$: 2] is equivalent to [0: 2], placing $ on the right side of a range expression, then $ will represent the minimum value [1: $] is equivalent to [1: 2].
2.5 Associative arrays
If you just need to model a processor with several G-byte addressing ranges. In a typical test, this processor may only access hundreds or thousands of bytes used to store executable code and data. In this case, the allocation and initialization of a few G bytes of storage space is obviously wasteful.
The emulator generally uses a 32-bit address line or 64-bit data as the indexed data packet. Obviously, this has a certain extra cost.
Associative arrays are declared by placing data types in square brackets。
module test_enum();
bit[63:0] assoc[bit[63:0]],idx=1; //64个bit[63:0] 关联数组assoc
repeat(64) begin //对1,2,4,8,16等等的稀疏元素进行初始化。
assoc[idx]=idx;
idx=idx<<1;
end
foreach(assoc[i]) //foreach遍历数组
$display("assoc[%0d]=%0d",i,assoc[i]);
if(assoc.first(idx)) //使用函数遍历数组
begin //得到第一个索引
do
$display("assoc[%h]=%h",idx,assoc[idx]);
while(assoc.next(idx)); //得到下一个索引
end
assoc.first(idx); //找到并删除第一个元素
assoc.delete(idx);
$display("the array now has %0d elements",assoc.num);
end
endmodule
