Verification of ATM switches requires the test platform to generate constrained random incentives and collect functional coverage data.
The top floor design becomes squat.
The environment class is the core of the test platform. This class contains the various modules of the layered test platform, such as generators, drivers, monitors and scoreboards. It also controls the four steps of the test: generating a random configuration, establishing a test platform operating environment, running and waiting for the test to end, and closing the system and closing the report.
To build a complete verification environment with System Verilog, the core lies in the use of callback functions and blueprint patterns, which can be said to be the callback mechanism and blueprint mechanism.
Building a complete verification environment on the basis of System Verilog provides three mechanisms: Sequence mechanism, factory mechanism and callback mechanism. Among them, the sequence mechanism and the factory mechanism are an extension of System Verilog's blueprint mechanism.
