6.11 Constraint techniques and techniques
6.11.1 Constraints using variables
Use random variables to set upper bound constraints when assigning values randomly.
Example 6.33. Using variables to set upper bound constraints
class bounds；
rand int size；
int max_size=100;
constraint c_size {
size inside {[1:max_size]};
}
endclass
By changing the value of the variable max_size, the upper limit of the random variable size can be changed.
Using variables in dist constraints can enable or disable certain values or ranges.
Example 6.34. Dist constraint with weighted variables
typedef enum {READ8， READ16，READ32} read_e;
class ReadCommands;
rand read_e read_cmd;
int read8_wt=1, read16_wt=1, read32_wt=1;
constraint c_read {READ8:=read8_wt,
READ16:=read16_wt,
READ32:=read32_wt};
}
endclass
By changing the value of the read8_wt weight variable, the probability of the constraint generating command can be changed. More importantly, certain commands can be prohibited by setting the weight to 0.
6.11.2 Using non-random values
If a set of constraints has generated almost all the desired excitation vectors during the randomization process, but there are still a few types of excitation vectors, you can call the randomiz () function first and then use Set the value to a fixed expected value to resolve. The fixed excitation value set can violate the relevant constraints.
If only a few variables need to be modified, you can use the rand_mode () function to set these variables to non-random variables.
Example 6.35 Use rand_mode () to prohibit randomization of variables SV Green Paper P155
p.length.rand_mode (0); // Set the packet length to a non-random value
p.length = 42; // Set the packet length to a constant
6.11.3 Checking the validity of values with constraints
After randomizing an object and changing the values of its variables, you can check whether the object is still valid by checking whether the values obey the constraints. When calling the handle.randomize (null) function, System Verilog treats all variables as non-random variables and only checks whether these variables meet the constraints.
6.11.4 Randomize individual variables When you
call randomize (), only a subset of variables are passed, and only a few variables in the class are randomized.
6.11.5 Turning constraints on or off
Use conditional operators (-> or if-else) to construct constraints controlled by non-random variables.
A more common method is to establish an independent set of constraints for each instruction, and close all other constraints when in use.
6.11.6 Using inline constraints
during testing 6.11.7 Using external constraints during testing
can define a class in a file, this class has only one empty constraint, and then define the different constraints in each different test Version to generate different incentives.
6.12 Common mistakes in randomization
6.12.1 Be careful with signed variables
Do not use signed types in random constraints unless necessary.
6.12.2 Tips for improving the performance of the solver
Avoid using complex operations such as division, multiplication, and modulus.
6.13 Iteration and array constraints
6.14 Generate atomic excitations and scenarios
How to generate random transaction sequences?
Random sequence randsequence
array of random objects
6.15 Random control
6.16 Random number generator
6.17 Random device configuration
6.18 Conclusion
CRT (constrained random testing) is the only feasible way to generate the stimulus needed to verify complex designs. System Verilog provides multiple methods for generating random excitations.
