1. Clock module
The nominal operating clock frequency of the 28335 DSP is 150MHz. High clock frequency will inevitably bring electromagnetic interference . In order to reduce electromagnetic interference, the output frequency of the crystal oscillator must be reduced. Here is the concept of "frequency division and frequency multiplication". It is with division and frequency multiplication that it is easier to obtain various frequencies. The multiples of 28335 frequency division and frequency multiplication range from 0.25 to 10 times, and the built-in crystal oscillator is 30MHz (mine is like this, everyone’s may be different), if you want to get 150MHz, you can first divide by two and then ten times Frequency, you can get 150MHZ. The benefits of doing so can not only effectively reduce electromagnetic interference, but also reduce the manufacturing cost of the crystal oscillator . Some people may ask, is it necessary to use a 30MHz crystal oscillator? Can other crystal oscillators (such as 20MHz) be used? Theoretically, it is possible, but the frequency division is generally 1/2 to the power of n, and the multiplication frequency is generally an integer, so choose the most suitable crystal oscillator.
1. The clock circuit is an important part of the microprocessor circuit system and the benchmark for its operation. The clock sources used by the modules inside the TMS320F2833x DSP processor are different, and there are mainly 5 types of clock signals:
- External crystal (crystal oscillator) : The clock signal provided through XCLKIN/X1 through pins X1, X2 or external clock, the clock signal is recorded as OSCCLK.
- OSCCLK passes through the phase-locked loop (PLL) module or directly sent to the CPU. This clock signal is the CPU clock input and is denoted as CLKIN.
- After CLKIN is input to the CPU, the CPU outputs it, which is called CPU clock output or system output clock, and is denoted as SYSCLKOUT. SYSCLKOUT has the same frequency as CLKIN.
- The high-speed peripheral clock HSPCLK used by the on - chip peripherals . This clock signal is obtained by dividing the frequency of the CPU clock SYSCLKOUT.
- Low-speed peripheral clock LSPCLK used by on - chip peripherals . This clock signal is obtained by dividing the frequency of the CPU clock SYSCLKOUT.
2. The composition of the clock module:
- PLL (Phased Lock Loop);
- Crystal oscillator (Crystal Oscillator);
- Clock Monitor Circuit (Clock Monitor Circuit);
- Clock Enable Circuit (Clock Enable Circuit).
3. Crystal oscillator and PLL module
F2833x series DSP can provide clock through external crystal oscillator and external clock signal, and provide the system to the system after frequency multiplication through internal phase-locked loop loop. Users can calculate the required frequency multiplication factor according to the actual operating frequency, and set the PLL frequency multiplication factor through software. The following figure shows the generation of the on-chip peripheral clock.
4. PLL-based clock module
The F2833x chip has an on-chip PLL-based clock module, which has a 4-bit proportional control register that can select different clock frequencies for the CPU. The following is the structure diagram of the oscillator and PLL module:
The PLL-based clock module can provide the following two operating modes:
1) Crystal oscillator operation. The on-chip oscillator allows the use of an external crystal oscillator to provide a time reference for the chip. The crystal oscillator is connected to the X1 and X2 pins, and the XCLKIN pin is pulled low.
2) External clock source operation. If the on-chip oscillator is not used, this mode allows the internal oscillator to be bypassed, and the chip clock is generated from an external clock source on the X1 pin or XCLKIN pin.
- PLL control register PLLCR
- Peripheral clock control register PCLKCR0, 1, 3
The PCLKCR0/1/3 register enables/disables the input clock signals of various peripheral modules. The write operation of the PCLKCR0/1/3 register will cause a delay of 2 SYSCLKOUT cycles. Because the peripheral GPIO is multiplexed, all peripherals cannot be used at the same time; however, it is possible to enable the clock of the peripherals at the same time, but this configuration is invalid.
- High-speed peripheral clock prescaler register (HISPCP)
- Low-speed peripheral clock prescaler register (LOSPCP)
- PLL status register (PLLSTS)
- Low power mode control register (LPMCR0)
2. Watchdog module
1. The function of the watchdog:
Watchdog (WatchDog, WD) is often used to monitor the execution of the program. As long as the 8-bit watchdog counter reaches its maximum value, the module will generate an interrupt or reset its processor. In order to avoid the above situation, the user must disable the counter or write the two data 0x55 and 0xAA in the program on time (the order cannot be reversed) the keyword register of the watchdog ("feed dog") to reset the watchdog counter .
2. Watchdog clock
After the external oscillator clock signal (OSCCLK) passes through the 512 frequency divider, it is divided by the watchdog frequency divider WDPS (2:0) to generate the WDCLK signal, which is the watchdog clock signal.
If the WDDIS bit in the watchdog control register WDCR is 0, WDCLK will be used as the counting clock of the watchdog counter register WDCNTR to make it count. When the 8-bit counter reaches the maximum value, the watchdog will generate an output pulse (/WDRST) or (/WDINT) interrupt signal (the width is 512 OSCCLK clock cycles).
3. The composition of the watchdog
- WD Counter
- Watchdog restart manager WD Reset Register
- Watchdog clock generator
- Watchdog status bit
4. Watchdog reset, interrupt mode
When the watchdog counter reaches the maximum value, the watchdog will output a reset signal (/WDRST) or an interrupt signal (/WDINT). The former will cause the zinc chip to reset, and the latter will issue an interrupt request.
1) Reset mode. When the watchdog counter reaches the maximum value, it will output (/WDRST) reset signal, which will pull the chip reset pin (/XRS) low and maintain 512 OSCCLK cycles.
2) Interrupt mode. When the watchdog counter reaches the maximum value, an interrupt signal (/WDINT) will be output, which will be pulled low and maintained for 512 OSCCLK cycles; if the interrupt is enabled in the PIE interrupt, WAKEPIE will be responded by PIE. The watchdog interrupt is triggered by the falling edge of the /WDINT signal, so if the WAKEINT interrupt is enabled before the /WDINT signal becomes invalid, the program will not immediately enter the next WAKEINT interrupt; the next WAKEINT interrupt will occur the next time Occurs when the watchdog overflows.
If the watchdog is configured from interrupt mode to reset mode while /WDINT is still valid, it will cause the device to reset immediately. Before reconfiguring the watchdog into reset mode, you can read the WDINTS bit of the SCSR register to determine whether the current /WDINT signal is still in a valid state.
5. Related registers
- System Control and Status Register (SCSR)
WDINTS: Watchdog interrupt status bit; WDENINT: Watchdog interrupt enable bit; WDOVERRIDE: Watchdog protected bit
- Watchdog counting register (WDCNTR)
- Watchdog reset key register (WDKEY)
- Watchdog control register (WDCR)
*************************************************************************************************************************************************
The hardware part is over, the following is the software part
1. Example_2833xWatchdog.c [Watchdog experiment]
// TI File $Revision: /main/9 $
// Checkin $Date: April 21, 2008 15:43:50 $
//###########################################################################
//
// FILE: Example_2833xWatchdog.c
//
// TITLE: DSP2833x Watchdog interrupt test program.
//
// ASSUMPTIONS:
//
// This program requires the DSP2833x header files.
//
// As supplied, this project is configured for "boot to SARAM"
// operation. The 2833x Boot Mode table is shown below.
// For information on configuring the boot mode of an eZdsp,
// please refer to the documentation included with the eZdsp,
//
// $Boot_Table:
//
// GPIO87 GPIO86 GPIO85 GPIO84
// XA15 XA14 XA13 XA12
// PU PU PU PU
// ==========================================
// 1 1 1 1 Jump to Flash
// 1 1 1 0 SCI-A boot
// 1 1 0 1 SPI-A boot
// 1 1 0 0 I2C-A boot
// 1 0 1 1 eCAN-A boot
// 1 0 1 0 McBSP-A boot
// 1 0 0 1 Jump to XINTF x16
// 1 0 0 0 Jump to XINTF x32
// 0 1 1 1 Jump to OTP
// 0 1 1 0 Parallel GPIO I/O boot
// 0 1 0 1 Parallel XINTF boot
// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
// 0 0 1 1 Branch to check boot mode
// 0 0 1 0 Boot to flash, bypass ADC cal
// 0 0 0 1 Boot to SARAM, bypass ADC cal
// 0 0 0 0 Boot to SCI-A, bypass ADC cal
// Boot_Table_End$
//
// DESCRIPTION:
//
// This program exercises the watchdog.
//
// First the watchdog is connected to the WAKEINT interrupt of the
// PIE block. The code is then put into an infinite loop.
//
// The user can select to feed the watchdog key register or not
// by commenting one line of code in the infinite loop.
//
// If the watchdog key register is fed by the ServiceDog function
// then the WAKEINT interrupt is not taken. If the key register
// is not fed by the ServiceDog function then WAKEINT will be taken.
//
// Watch Variables:
// LoopCount for the number of times through the infinite loop
// WakeCount for the number of times through WAKEINT
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h" // Examples Include File
// Prototype statements for functions found within this file.
interrupt void wakeint_isr(void); //若PIE模块使能，看门狗中断模式时中断信号的中断子程序；
// Global variables for this example
Uint32 WakeCount;
Uint32 LoopCount;
void main(void) //主函数
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl(); 这部分重点看一下 //看门狗只有用到的时候才会在初始化程序中，这里有必要看一看，“Open Definitions”，下面是我拿过来的初始化函数，大家可以分析一下。
void InitSysCtrl(void)
{
// Disable the watchdog
DisableDog(); //关闭看门狗
// Initialize the PLL control: PLLCR and DIVSEL
// DSP28_PLLCR and DSP28_DIVSEL are defined in DSP2833x_Examples.h
InitPll(DSP28_PLLCR,DSP28_DIVSEL); //初始化PLL模块，初始化这部分大家看看上面理论部分的PLL修改流程图，然后看看Initpll（）函数内部.这里也稍作解释，DSP28_PLLCR变量和DSP28_DIVSEL变量可以用“Open Declarations”来看，DSP28_PLLCR=10,DSP28_DIVSEL=2，即对OSCCLK系统时钟进行10倍频和2分频获得150MHz的SYSCLKOUT或CLKIN给看门狗使用。
// Initialize the peripheral clocks
InitPeripheralClocks(); //初始化外设时钟，可以“Open Definitions”看看函数的作用。我这里直接写出来：将高速外设时钟=SYSCLKOUT/2，低速外设时钟=SYSCLKOUT/4，这部分也能使能/禁止所有外设的时钟
}
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to //以上系统初始化；
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.WAKEINT = &wakeint_isr; //将中断子程序的初始地址指向中断向量表（由于中断向量表是被写保护的，所以在开头和结尾要分别加上EALLOW和EDIS）
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// Step 5. User specific code, enable interrupts:
// Clear the counters
WakeCount = 0; // Count interrupts //记录看门狗中断次数；
LoopCount = 0; // Count times through idle loop //记录看门狗空循环次数；
// Connect the watchdog to the WAKEINT interrupt of the PIE
// Write to the whole SCSR register to avoid clearing WDOVERRIDE bit
EALLOW;
SysCtrlRegs.SCSR = BIT1; //配置看门狗系统控制和状态寄存器，具体BIT的值可以“Open Declarations”，在这里BIT1=0x0002，即看门狗中断使能，看门狗工作在中断模式；
EDIS;
// Enable WAKEINT in the PIE: Group 1 interrupt 8
// Enable INT1 which is connected to WAKEINT:
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block //PIE开中断
PieCtrlRegs.PIEIER1.bit.INTx8 = 1; // Enable PIE Gropu 1 INT8 //看门狗中断信号GROUP1 interrupt 8
IER |= M_INT1; // Enable CPU int1 //使能CPU 通道1
EINT; // Enable Global Interrupts //全局开中断
// Reset the watchdog counter
ServiceDog(); //看门狗程序，想要查看具体函数可以“Open Definitions”，这里是定时向看门狗复位关键字寄存器写入0xAA和0x55
// Enable the watchdog
EALLOW;
SysCtrlRegs.WDCR = 0x0028; //配置看门狗控制寄存器0x0010 1000，看门狗检查位WDCHK，必须为101；写入其他只会导致看门狗立即产生复位或中断
EDIS;
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
LoopCount++;
// Uncomment ServiceDog to just loop here
// Comment ServiceDog to take the WAKEINT instead
ServiceDog(); //“喂狗”程序，在中断（溢出）之前清零看门狗计数器
}
}
// Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here:
// If local ISRs are used, reassign vector addresses in vector table as
// shown in Step 5
interrupt void wakeint_isr(void)
{
WakeCount++; //正是因为有“喂狗”程序，所以中断程序应该不会被执行
// Acknowledge this interrupt to get more from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
//===========================================================================
// No more.
//===========================================================================
After the programming explained above, the simulation starts below. (For specific loading projects, please see [Lecture 7] Creating Project Section)
Because there is a "feeding dog" program here, the watchdog counter will be cleared regularly, so no interrupt signal will be sent, and the interrupt subroutine will not be executed. Here we monitor the variables LoopCount and WakeLoop. The correct phenomenon should be LoopCount keeps increasing by itself, and WakeCount is always 0.
After running:
Second run:
Alright, the end of this lecture~