F28335 ADC module
ADC conversion module
The A/D converter (ADC) usually goes through four steps to convert an analog quantity into a digital quantity: sampling, holding, quantizing and encoding.
Sampling : Convert an analog quantity that changes continuously in time into an analog quantity that changes discretely in time.
Hold : Store the sampling results until the next sampling. This process is called hold. Generally, the sampler and the hold circuit are collectively referred to as a sample and hold circuit.
Quantization : The sampling level is normalized to a discrete digital level close to it. This process is called quantization.
ADC key indicators
Resolution : refers to the amount of change of the analog signal when the digital value changes by a minimum amount, defined as the ratio of full scale to 2^n. Resolution is also called accuracy, and is usually expressed in terms of the number of bits of a digital signal. The popular explanation resolution is to determine the minimum sampling value. For example, the reference voltage is 1V, and the sampling value of 8 bits is 1/256. 1 means that the minimum sampling value is 1/1024. The higher the resolution, the more accurate the sampling.
Conversion rate : It can also be called the AD sampling rate, which is the reciprocal of the time required for one AD conversion.
Sampling time : refers to the interval between two conversions. In order to ensure the correct completion of the conversion, the sampling rate must be less than or equal to the conversion rate.
Quantization error : the error caused by the finite resolution of AD, that is, the maximum deviation between the stepped transfer characteristic curve of finite resolution AD and the transfer characteristic curve of infinite resolution AD.
Illustrate the above four indicators:
For example, the AD conversion module of F28335 is 12-bit, the maximum clock frequency of AD is 25MHz, and the sampling rate is 12.5Msps.
If you want to sample a 1V voltage, the resolution = 1/2 to the 12th power = 1/4096,
Conversion rate: set in the program according to your needs,
Maximum sampling rate=1/12.5M=80ns (also can be set by setting the clock)
Quantization error: The voltage conversion between each code represents 1/4096V, and 1/8192V voltage cannot be collected. In other words, there is an error between the actual voltage generating the specified code and the voltage representing the code.
ADC single channel single sampling code + comment
1. CON0 port sampling
2. Output 7 decimal places sampling voltage
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
// Determine when the shift to right justify the data takes place
// Only one of these should be defined as 1.
// The other two should be defined as 0.
#define POST_SHIFT 0 // Shift results after the entire sample table is full
#define INLINE_SHIFT 1 // Shift results as the data is taken from the results regsiter
#define NO_SHIFT 0 // Do not shift the results
// ADC start parameters
#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
#endif
#define ADC_CKPS 0x0 // ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz
#define ADC_SHCLK 0x1 // S/H width in ADC module periods = 2 ADC cycle
#define AVG 1000 // Average sample limit
#define ZOFFSET 0x00 // Average Zero offset
#define BUF_SIZE 2 // Sample buffer size
// Global variable for this example
volatile Uint16 SampleTable[BUF_SIZE];
volatile float adc0=0;
main()
{
Uint16 i;
// Uint16 adc=0;
Uint16 array_index;
InitSysCtrl();
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // 系统外设时钟6分频，一般ADC就用6分频
// 这是因为ADC最高只能配置25MHz的频率
// 所以最快转换一次的时间使80ns
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
InitAdc(); //这个初始化程序，必须添加DSP2833x_Adc.C文件
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; //ADC采样时间选择
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; //ADC内核分频
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; //级联工作方式
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x1; //设置CONV0 为第一个通道
AdcRegs.ADCTRL1.bit.CONT_RUN = 0; //连续运行模式
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1; //完成排序后，排序器指针回到最初状态
AdcRegs.ADCCHSELSEQ1.all = 0x0; //初始化SEQ1排序寄存器
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x0; // 设置一对转换，共16通道
// Clear SampleTable
for (i=0; i<BUF_SIZE; i++)
{
SampleTable[i] = 0;
}
// Start SEQ1
AdcRegs.ADCTRL2.all = 0x2000; //软件启动转换功能
while(1)
{
if(array_index>2)
array_index = 0;
while(AdcRegs.ADCST.bit.INT_SEQ1 == 0); //等待ADC的中断位为1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; //清楚排序器中断位
SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)>>4); //将结果寄存器16位的值转换位10进制数
adc0=(float)SampleTable[0] * 3.0 /4096.0; // 转换为我们读取的数据类型
// 数据类型转换另外一篇有说明
DELAY_US(100);
}
}
//===========================================================================
// No more.
//===========================================================================
ADC multi-channel continuous sampling code + comment
1. CONV00 CONV01 CONV02 Three-channel sampling
2. Continuous sampling
Different from single channel only in configuration and data extraction
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#define POST_SHIFT 0 // Shift results after the entire sample table is full
#define INLINE_SHIFT 1 // Shift results as the data is taken from the results regsiter
#define NO_SHIFT 0 // Do not shift the results
#if (CPU_FRQ_150MHZ) // Default - 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3) = 25.0 MHz
#endif
#if (CPU_FRQ_100MHZ)
#define ADC_MODCLK 0x2 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 100/(2*2) = 25.0 MHz
#endif
#define ADC_CKPS 0x0 // ADC module clock = HSPCLK/1 = 25.5MHz/(1) = 25.0 MHz
#define ADC_SHCLK 0x1 // S/H width in ADC module periods = 2 ADC cycle
#define AVG 1000 // Average sample limit
#define ZOFFSET 0x00 // Average Zero offset
#define BUF_SIZE 6 // Sample buffer size
// Global variable for this example
volatile Uint16 SampleTable[BUF_SIZE];
volatile float adc0=0;
volatile float adc1=0;
volatile float adc2=0;
main()
{
Uint16 i;
Uint16 array_index;
InitSysCtrl();
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // 系统外设时钟6分频，一般ADC就用6分频
// 这是因为ADC最高只能配置25MHz的频率
// 所以最快转换一次的时间使80ns
EDIS;
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
InitAdc(); //这个初始化程序，必须添加DSP2833x_Adc.C文件
AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK; //ADC采样时间选择
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS; //ADC内核分频
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; //级联工作方式
AdcRegs.ADCTRL3.bit.SMODE_SEL= 0; // 顺序采样
AdcRegs.ADCTRL1.bit.CONT_RUN = 1; //连续采样
AdcRegs.ADCTRL1.bit.SEQ_OVRD = 1 ; //完成排序后，排序器指针回到最初状态
AdcRegs.ADCMAXCONV.bit.MAX_CONV1 = 0x2;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1 ;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2 ;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1; //允许向CPU发出中断请求
// Clear SampleTable
for (i=0; i<BUF_SIZE; i++)
{
SampleTable[i] = 0;
}
AdcRegs.ADCTRL2.bit.SOC_SEQ1=1; //软件启动转换功能
while(1)
{
if(array_index>BUF_SIZE)
array_index = 0;
while(AdcRegs.ADCST.bit.INT_SEQ1 == 0); //等待ADC的中断位为1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; //清楚排序器中断位
SampleTable[array_index++]= ( (AdcRegs.ADCRESULT0)>>4);
SampleTable[array_index++]= ( (AdcRegs.ADCRESULT1)>>4);
SampleTable[array_index++]= ( (AdcRegs.ADCRESULT2)>>4);
adc0=(float)SampleTable[0] * 3.0 /4096.0; // 转换为我们读取的数据类型
adc1=(float)SampleTable[1] * 3.0 /4096.0; // 数据类型转换另外一篇有说明
adc2=(float)SampleTable[2] * 3.0 /4096.0;
DELAY_US(100);
}
}
//===========================================================================
// No more.
//===========================================================================