1. Interrupt overview
1.1 Interrupt response mechanism and classification
When the CPU is processing normal programs, it is sometimes required to process tasks with higher demand levels, so it has to interrupt the current task process and enter the interrupt service routine. After processing these additional tasks, you need to return to the previous task. Therefore, you must save the scene before entering the interrupt program to ensure that you can accurately return to the previous task after the main task is interrupted and the interrupt program is completed. Task node.
Interrupt requests can be divided into:
- Maskable interrupt: can be processed by judging priority
- Non-maskable interrupt: forcibly stop the CPU process and enter the interrupt program, such as reset and NMI.
Interrupt sources can also be divided into two categories:
- On-chip internal interrupt sources: PWM, CAP, QEP, timer, etc.
- Chip external interrupt source: signals introduced by external interrupt input pins XINT1 and XINT2
1.2 Interrupt structure
F28335 has a lot of peripheral resources. These peripheral resources may release additional tasks to the CPU at the same time. In other words, there are many interrupt sources of F28335. If these interrupt sources want the response of the CPU, they must transmit signals through the interrupt line. To the CPU. However, the number of interrupt lines of F28335 is limited. At this time, the PIE module allocates interrupt resources.
As can be seen from the figure,
- External interrupt sources are judged and processed through the PIE module
- Among the internal interrupt sources, Timer 1 and Timer 2 are processed through INT13 and INT14 separately, and others are also processed through the PIE module
- PIE module handles INT~INT12
- A total of 16 interrupt lines
2. Interrupt management module PIE
The function of the PIE module is to manage the triggering of multiple interrupt sources in the case of limited interrupt lines.
2.1 PIE module structure
The structure of the PIE is shown in the figure above. The PIE module is composed of multiple interrupt groups and a multiplexer for each interrupt group. From INT1 to INT12 are maskable interrupts managed by the PIE module, and each of these 12 interrupts is composed of 8 externally designed interrupts. For example, INT1.X corresponds to INT1.1~INT1.8 on the way. A peripheral-level interrupt is our corresponding external interrupt source pin.
The PIE module groups these 8 peripheral interrupts into a group through an 8-to-1 multiplexer. When we configure in the program, we also configure it based on this structure.
Supplement the priority of PIE response
- INT1>INT2>...>INT12
- INT1.1>INT1.2>...>INT1.8
2.2 Response mechanism of PIE module
The PIE module has so many peripherals to be managed, so there must be corresponding response sequences and registers that need to be configured.
In the PIE module, each group of interrupts has a corresponding interrupt flag (PIEIFRx) and an enable bit (PIEIERx.y). In addition, each group of PIE interrupts (INT1~INT12) has a response flag (PIEACK). The following figure shows the operation flow of PIE hardware with different settings of PIEIFR and PIEIER.
Once the PIE controller generates an interrupt, the corresponding interrupt flag bit (PIEIFRx.y) will be set. If the corresponding PIE interrupt enable bit is also set to 1, the PIE will check the corresponding PIEACKx to determine whether the CPU is ready to respond to the interrupt. If the corresponding PIEACKx bit is cleared, PIE applies to the CPU for an interrupt; if PIEACKx is set to 1, PIE will wait until the corresponding PIEACKx is cleared before applying for an interrupt to the CPU. PIE controls the PIEACKx bit to control that only one interrupt in each group can be responded. Once the response is made, the PIEACKx response needs to be cleared to zero so that it can respond to the interrupt from the back of the group.
For example, if you want the CPU to respond to INT1.1 interrupts.
Just need
- PIEIFR1.1 logo position 1
- PIEIFR1.1 enable bit 1
- PIEIFR1.1 response flag bit 1
- IFR global flag position 1 (only for INT1~INT12)
- IER global interrupt enable is set to 1 (only for INT1~INT12)
2.3 Interrupt vector table
Since the address corresponding to each interrupt source of F28335 is set in advance, we cannot change it, so an interrupt vector table must be prepared.
It can be seen from the figure
- Each of INT1~INT12 corresponds to 8 external interrupts
- There are 96 responsive resources in total, and there are many rich resources
2.4 Simple example of interrupt configuration
The configuration of the interrupt is completely corresponding to the response mechanism of the PIE module.
Configure the external interrupt XINT1.
first step:
After basic initialization, specify the PIE module, generally in InitPieVectTable(); specify after the PIE module is initialized.
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.XINT1 = &xint1_isr;
EDIS;
}The second step:
Turn on the clock of the PIE module. After querying the interrupt vector table, we know that the external interrupt XINT1 is enabled at INT1.4. Turn on this interrupt enable.
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW;
PieVectTable.XINT1 = &xint1_isr; //赋予中断地址
EDIS;
IER |= M_INT1; //全局使能INT1
PieCtrlRegs.PIEIER1.bit.INTx4 = 1; //使能INT1.4
EINT;
ERTM;
}At that time, I was wondering where the PIEIFR flag went to 1. In fact, it was automatically set to 1 when the interrupt was responded. We only need to enable it so that he can pass smoothly.
The third step:
Write the function in our interrupt, and clear the interrupt response flag PIEACK in the interrupt.
interrupt void xint1_isr(void)
{
Xint1Count++;
GpioDataRegs.GPACLEAR.all = 0x4;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}