Differential clock module

// generate 200MHz differential clock:

// writing a:

module sim_top;
reg clk;
initial
begin
　　clk <= 1'b0;
end
always #5 clk=~clk;
system system(
　　.clk_in1_p(clk),
　　.clk_in1_n(~clk)
　　);
endmodule

 

// writing II:

module sim_top(

);

reg clk_in1_p;

wire clk_in1_n;

assign clk_in1_n = ~clk_in1_p;

initial clk_in1_p = 0;

always #5 clk_in1_p <= ~clk_in1_p;

system system(
　　.clk_in1_p(clk_in1_p),
　　.clk_in1_n(clk_in1_n) 
　　); 
endmodule