Software simulation protocol : use the CPU to directly control the level of the communication pin (GPIO) to generate logic that conforms to the communication protocol standard.
Hardware implementation protocol : The I2C on-chip peripheral of STM32 is specially responsible for implementing the I2C communication protocol. As long as the peripheral is configured, it will automatically generate communication signals according to the protocol requirements, send and receive data and cache them. The CPU only needs to detect the status of the peripheral And access the data register, you can complete the data transmission and reception. This way of handling the I2C protocol by the hardware peripherals relieves the CPU and makes software design simpler.
The I2C peripheral of STM32 can be used as the master and slave for communication, supports 100Kbit/s and 400Kbit/s rates, supports 7-bit and 10-bit device addresses, supports DMA data transmission, and has data verification functions.
STM32 frame structure
1. Communication pins
The STM32 chip has multiple I2C peripherals, and their I2C communication signals are led out to different GPIO pins. These designated pins must be configured when used, and the "STM32F10x Specifications" shall prevail.
2. Clock control logic
The clock signal of the SCL line is controlled by the I2C interface according to the clock control register (CCR), and the controlled parameter is mainly the clock frequency.
• The "standard/fast" mode of I2C communication can be selected, and these two modes correspond to the communication rate of 100/400Kbit/s for I2C respectively.
• The duty cycle of the SCL clock can be selected in the fast mode, and the Tlow/Thigh=2 or Tlow/Thigh=16/9 modes can be selected.
• The 12-bit configuration factor CCR in the CCR register, which works with the input clock source of the I2C peripheral to generate the SCL clock. The I2C peripheral input clock source of STM32 is PCLK1.
Calculate the clock frequency:
Standard Mode: Thigh=CCR*TPCKL1 Tlow = CCR*TPCLK1
When Tlow/Thigh=2 in fast mode: Thigh = CCR*TPCKL1 Tlow = 2*CCR*TPCKL1
When Tlow/Thigh=16/9 in fast mode: Thigh = 9*CCR*TPCKL1 Tlow = 16*CCR*TPCKL1
For example, our PCLK1=36MHz, and we want to configure the rate of 400Kbit/s, the calculation method is as follows:
PCLK clock period: TPCLK1 = 1/36000000
Target SCL Clock Period: TSCL = 1/400000
High time in SCL clock cycle: THIGH = TSCL/3
Low time in SCL clock cycle: TLOW = 2*TSCL/3
Calculate the value of CCR: CCR = THIGH/TPCLK1 = 30
The calculated CCR value can be written to the register.
3. Data control logic
The SDA signal of I2C is mainly connected to the data shift register. The data source and destination of the data shift register are the data register (DR), the address register (OAR), the PEC register and the SDA data line.
• When sending data to the outside, the data shift register uses the "data register" as the data source, and sends the data bit by bit through the SDA signal line;
• When receiving data from the outside, the data shift register stores the data sampled by the SDA signal line into the "data register" bit by bit.
4. Overall control logic
The overall control logic is responsible for coordinating the entire I2C peripheral, and the working mode of the control logic changes according to the parameters of the "Control Register (CR1/CR2)" we configure.
When the peripheral is working, the control logic will modify the "status register (SR1 and SR2)" according to the working state of the peripheral. Just read the relevant register bits of these registers, you can know the working state of I2C.