[STM32] DAC detailed

00. Table of Contents

01. Introduction to DAC

The DAC module is a 12-bit voltage output digital-to-analog converter. The DAC can be configured in 8-bit or 12-bit mode and can be used with a DMA controller. In 12-bit mode, the data can be left-justified or right-justified. The DAC has two output channels, and each channel has a converter. In the DAC dual-channel mode, each channel can be converted separately; when two channels are combined to perform the update operation simultaneously, the conversion can also be performed at the same time. The resolution can be improved by an input reference voltage pin V REF+ (shared with ADC).

02. DAC main features

● Two DAC converters: each corresponding to one output channel
● Data is left-aligned or right-aligned in 12-bit mode
● Synchronous update function
● Noise wave
generation ● Triangular wave generation
● DAC dual channel conversion separately or simultaneously
● Each channel has DMA Functions
● DMA underflow error detection
● Conversion by external trigger signal
● Input reference voltage V REF+

Tips

After enabling DAC channel x, the corresponding GPIO pin (PA4 or PA5) will be automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic current consumption, you should first configure the PA4 or PA5 pin to analog mode (AIN).

03. DAC function description

DAC channel enable

Set the corresponding ENx bit in the DAC_CR register to 1 to turn on the corresponding DAC channel. After a period of startup time t WAKEUP, the DAC channel is truly enabled.

DAC output buffer enable

The DAC integrates two output buffers, which can be used to reduce the output impedance and directly drive an external load without adding an external operational amplifier. Through the corresponding BOFFx bit in the DAC_CR register, each DAC channel output buffer can be enabled or disabled.

DAC data format

According to the selected configuration mode, data must be written to the specified register as follows:
● For DAC single channel x, there are three possible ways:
— 8-bit right-justified: software must load data into DAC_DHR8Rx [7:0] bits (store To DHRx[11:4] bits).
— 12-bit left-justified: software must load data into DAC_DHR12Lx[15:4] bits (stored in DHRx[11:0] bits).
— 12-bit right-justified: software must load data into DAC_DHR12Rx[11:0] bits (stored in DHRx[11:0] bits).

DAC conversion

DAC_DORx cannot be written directly, any data must be loaded into the DAC_DHRx register (write DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD) before it can be transferred to DAC channel x.

If the hardware trigger is not selected (the TENx bit in the DAC_CR register is reset), the data stored in the DAC_DHRx register will be automatically transferred to the DAC_DORx register after one APB1 clock cycle. However, if the hardware trigger is selected (the TENx bit in the DAC_CR register is set) and the trigger condition comes, the transfer will take place after three APB1 clock
cycles.

When DAC_DORx is loaded with the content of DAC_DHRx, the analog output voltage will be available after a period of t SETTLING, which depends on the power supply voltage and the analog output load.

DAC output voltage

After linear conversion, the digital input will be converted to an output voltage between 0 and V REF+. The analog output voltage of each DAC channel pin is determined by the following formula:

DAC trigger selection

If the TENx control bit is 1, the conversion can be triggered by external events (timer counter, external interrupt line). The TSELx[2:0] control bits will determine which of the eight possible events will trigger the conversion, as shown in Table 58.

DMA request

Each DAC channel has DMA function. Two DMA channels are used to process the DMA request of the DAC channel. When the DMAENx bit is set, if an external trigger (rather than a software trigger) occurs, a DAC DMA request will be generated. The value of the DAC_DHRx register is then transferred to the DAC_DORx register.

In dual channel mode, if both DMAENx bits are set to 1, two DMA requests will be generated. If only one DMA request is required, only the corresponding DMAENx bit should be set. In this way, the application can manage two DAC channels through a DMA request and a specific DMA channel in dual channel mode.

Generate triangle waves

A small triangular wave can be superimposed on a direct current or slow-changing signal. Set WAVEx[1:0] to “10” to select DAC to generate triangle wave. The amplitude is configured by the MAMPx[3:0] bits in the DAC_CR register. After each trigger event, after three APB1 clock cycles, the internal triangle wave counter will increment. In the case of no overflow, the value of this counter will be added to the contents of the DAC_DHRx register, and the resulting sum will be stored in the DAC_DORx register. As long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits, the triangle wave counter will keep incrementing. Once the configured amplitude is reached, the counter will decrement to zero, then increment, and so on. The triangular wave generation function can be turned off by resetting the WAVEx[1:0] bits.

04. DAC dual channel conversion

In order to effectively utilize the bus bandwidth in applications that require two DAC channels at the same time, the DAC module implements three dual registers: DHR8RD, DHR12RD and DHR12LD. In this way, two DAC channels can be driven simultaneously with only one register access.

11 conversion modes can be realized through two DAC channels and these three dual registers. But if required, all these conversion modes can also be implemented through separate DHRx registers. The following paragraphs will introduce all these modes.

Independent trigger (no waveform generated)

To configure the DAC to this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to different values, To configure different trigger sources
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When the
DAC 1 channel trigger signal arrives, the contents of the DHR1 register are transferred to DAC_DOR1 (after three APB1 clock cycles).
When the DAC 2 channel trigger signal arrives, the contents of the DHR2 register are transferred to DAC_DOR2 (after three APB1 clock cycles).

Independent trigger (generate a single LFSR)

To configure the DAC to this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to different values, To configure different trigger sources
● Set the WAVEx[1:0] of the two DAC channels to “01” and configure the same LFSR mask value in the MAMPx[3:0] bits
● Load the DAC dual-channel data to The required DHR register (DHR12RD, DHR12LD or DHR8RD) when the DAC channel 1 trigger signal arrives, the contents of the LFSR1 counter (using the same mask) and the contents of the DHR1 register are added, and the resulting sum is transferred to DAC_DOR1 (after three APB1 clock cycles) . The LFSR1 counter is then updated. When the DAC channel 2 trigger signal arrives, the contents of the LFSR2 counter (using the same mask) and the contents of the DHR2 register are added, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The LFSR2 counter is then updated.

Independent trigger (generate different LFSR)

To configure the DAC to this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to different values, To configure different trigger sources
● Set the WAVEx[1:0] of the two DAC channels to "01", and set different LFSR mask values ​​in the MAMP1[3:0] and MAMP2[3:0] bits
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When the
DAC channel 1 trigger signal arrives, the contents of the LFSR1 counter (using the mask configured by MAMP1[3:0]) are added to the contents of the DHR1 register, and the result is The sum is transferred to DAC_DOR1 (after three APB1 clock cycles). The LFSR1 counter is then updated.
When the DAC channel 2 trigger signal arrives, the contents of the LFSR2 counter (using the mask configured by MAMP2[3:0]) and the contents of the DHR2 register are added, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The LFSR2 counter is then updated.

Independent trigger (generate a single triangle wave)

To configure the DAC to this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to different values, To configure different trigger sources

● Set the WAVEx[1:0] of the two DAC channels to “1x”, and configure the same maximum amplitude value in the MAMPx[3:0] bits
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When the
trigger signal of DAC channel 1 arrives, the contents of the triangle wave counter of DAC 1 channel (using the same triangle wave amplitude) are added to the contents of the DHR1 register, and the resulting sum is transferred to DAC_DOR1 (after three APB1 clock cycles).
The DAC 1 channel triangle wave counter is updated immediately.
When the DAC 2 channel trigger signal arrives, the content of the DAC 2 channel triangle wave counter (using the same triangle wave amplitude) is added to the DHR2 register content, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles).
The DAC 2 channel triangle wave counter is updated immediately.

Independent trigger (generate different triangle waves)

To configure the DAC to this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to different values, To configure different trigger sources
● Set the WAVEx[1:0] of the two DAC channels to “1x”, and set different maximum amplitude values ​​in the MAMP1[3:0] and MAMP2[3:0] bits
● Change Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When the
DAC 1 channel trigger signal arrives, the DAC 1 channel triangle wave counter content (using the triangular wave amplitude configured by MAMP1[3:0]) is added to the DHR1 register content , The resulting sum is transferred to DAC_DOR1 (after three APB1 clock cycles). The DAC 1 channel triangle wave counter is updated immediately.
When the DAC 2 channel trigger signal arrives, the content of the DAC 2 channel triangle wave counter (triangular wave amplitude configured using MAMP2[3:0]) is added to the DHR2 register content, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The DAC 2 channel triangle wave counter is updated immediately.

Sync software starts

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)
In this configuration, the contents of the DHR1 and DHR2 registers will be after one APB1 clock cycle Transfer to DAC_DOR1 and DAC_DOR2 respectively.

Synchronous trigger (no waveform generated)

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to the same value, In order to configure the same trigger source for the two DAC channels
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)
when the trigger signal arrives, the contents of the DHR1 and DHR2 registers will be transferred to DAC_DOR1 and DAC_DOR2 respectively ( After three APB1 clock cycles).

Synchronous trigger (generate a single LFSR)

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to the same value, In order to configure the same trigger source for the two DAC channels
● Set the WAVEx[1:0] of the two DAC channels to “01”, and configure the same LFSR mask value in the MAMPx[3:0] bits
● Set the DAC Two-channel data is loaded into the required DHR register (DHR12RD, DHR12LD or DHR8RD) when the trigger signal arrives, the contents of the LFSR1 counter (using the same mask) are added to the contents of the DHR1 register, and the resulting sum is transferred to DAC_DOR1 (three APB1 clock cycles) after that). The LFSR1 counter is then updated. At the same time, the contents of the LFSR2 counter (using the same mask) are added to the contents of the DHR2 register, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The LFSR2 counter is then updated.

Synchronous trigger (generate different LFSR)

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to the same value, In order to configure the same trigger source for the two DAC channels
● Set the WAVEx[1:0] of the two DAC channels to "01", and set different ones in the MAMP1[3:0] and MAMP2[3:0] bits LFSR mask value
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) when the
trigger signal arrives, the LFSR1 counter content (using the mask configured by MAMP1[3:0]) is added to the DHR1 register content , The resulting sum is transferred to DAC_DOR1 (after three APB1 clock cycles). The LFSR1 counter is then updated.
At the same time, the contents of the LFSR2 counter (using the mask configured by MAMP2[3:0]) are added to the contents of the DHR2 register, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The LFSR2 counter is then updated.

Synchronous trigger (generate a single triangle wave)

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to the same value, In order to configure the same trigger source for the two DAC channels
● Set the WAVEx[1:0] of the two DAC channels to “1x”, and configure the same maximum amplitude value in the MAMPx[3:0] bits
● Double the DAC When the channel data is loaded into the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)
, when the trigger signal arrives, the contents of the triangle wave counter of the DAC 1 channel (using the same triangle wave amplitude) are added to the contents of the DHR1 register, and the sum is transferred to DAC_DOR1 (three APB1 After the clock cycle). The DAC 1 channel triangle wave counter is updated immediately.
At the same time, the contents of the triangle wave counter of the DAC 2 channel (using the same triangle wave amplitude) are added to the contents of the DHR2 register, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The DAC 2 channel triangle wave counter is updated immediately.

Synchronous trigger (generate different triangle waves)

To configure the DAC for this conversion mode, the following sequence needs to be followed:
● Set the two DAC channel trigger enable bits TEN1 and TEN2 to 1
● Set TSEL1[2:0] and TSEL2[2:0] to the same value, In order to configure the same trigger source for the two DAC channels
● Set the WAVEx[1:0] of the two DAC channels to "1x", and set different ones in the MAMP1[3:0] and MAMP2[3:0] bits Maximum amplitude value
● Load the DAC dual-channel data to the required DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) when the
trigger signal arrives, DAC channel 1 triangle wave counter content (triangular wave amplitude configured with MAMP1[3:0]) and DHR1 register content Add and transfer the sum to DAC_DOR1 (after three APB1 clock cycles). DAC channel 1 triangle wave counter is updated immediately.
At the same time, the contents of the triangle wave counter of DAC channel 2 (triangular wave amplitude configured using MAMP2[3:0]) are added to the contents of the DHR2 register, and the resulting sum is transferred to DAC_DOR2 (after three APB1 clock cycles). The DAC channel 2 triangle wave counter is updated immediately.

05. DAC Register

5.1 DAC Control Register (DAC_CR)

DAC control register
offset address: 0x00
reset value: 0x0000 0000

5.2 DAC Software Trigger Register (DAC_SWTRIGR)

DAC software trigger register
offset address: 0x04
reset value: 0x0000 0000

5.3 DAC 1 channel 12-bit right-justified data holding register (DAC_DHR12R1)

DAC channel1 12-bit right-aligned data holding register
offset address: 0x08
Reset value: 0x0000 0000

5.4 DAC 1 channel 12-bit left-justified data holding register (DAC_DHR12L1)

DAC channel1 12-bit left aligned data holding register
offset address: 0x0C
reset value: 0x0000 0000

5.5 DAC 1 channel 8-bit right-justified data holding register (DAC_DHR8R1)

DAC channel1 8-bit right aligned data holding register
Offset address: 0x10
Reset value: 0x0000 0000

5.6 DAC 2 channel 12-bit right-justified data holding register (DAC_DHR12R2)

DAC channel2 12-bit right aligned data holding register
Offset address: 0x14
Reset value: 0x0000 0000

5.7 DAC 2 channel 12-bit left-justified data holding register (DAC_DHR12L2)

DAC channel2 12-bit left aligned data holding register
offset address: 0x18
reset value: 0x0000 0000

5.8 DAC 2 channel 8-bit right-justified data holding register (DAC_DHR8R2)

DAC channel2 8-bit right-aligned data holding register
offset address: 0x1C
reset value: 0x0000 0000

5.9 Dual DAC 12-bit right-justified data holding register (DAC_DHR12RD)

Dual DAC 12-bit right-aligned data holding register
offset address: 0x20
reset value: 0x0000 0000

5.10 Dual DAC 12-bit left-justified data holding register (DAC_DHR12LD)

DUAL DAC 12-bit left aligned data holding register
offset address: 0x24
reset value: 0x0000 0000

5.11 Dual DAC 8-bit right-justified data holding register (DAC_DHR8RD)

DUAL DAC 8-bit right aligned data holding register
Offset address: 0x28
Reset value: 0x0000 0000

5.12 DAC 1 channel data output register (DAC_DOR1)

DAC channel1 data output register
offset address: 0x2C
reset value: 0x0000 0000

5.13 DAC 2 channel data output register (DAC_DOR2)

DAC channel2 data output register
offset address: 0x30
Reset value: 0x0000 0000

5.14 DAC Status Register (DAC_SR)

DAC status register
offset address: 0x34
Reset value: 0x0000 0000

06. Appendix

6.1 [STM32] STM32 series tutorial summary

Website: [STM32] STM32 series tutorial summary

07. Statement

STM32F4xx English Reference Manual