One, the map.lds file
linker script file
Function: for the compiler to use, tell the compiler each segment, how to distribute
/*输出格式：32位可执行程序，小端对齐*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
/*输出架构：arm架构*/
OUTPUT_ARCH(arm)
/*入口：_start*/
ENTRY(_start)
/*段*/
SECTIONS
{
. = 0x00000000;/*入口地址*/
. = ALIGN(4);/*4字节对齐*/
.text :
{
./Objects/start.o(.text) /*第一个文件存放start.o文件，指定start.o位置*/
*(.text) /*其余文件没有要求，编译器随便放*/
}
. = ALIGN(4);
.rodata : /*只读数据段*/
{ *(.rodata) }
. = ALIGN(4);
.data : /*数据段*/
{ *(.data) }
. = ALIGN(4);
__bss_start = .;
.bss : /*.bss段*/
{ *(.bss) }
__bss_end__ = .;
}Second, compilation
1. Assembly instruction: The compiler compiles a compilation instruction to generate machine code, occupying code segment space
2. Pseudo-instruction: The pseudo-instruction itself is not an instruction, the compiler can compile and generate multiple instructions to complete the function of one instruction together
3. Pseudo-operations: Instruct the compiler how to compile the code, all pseudo-operations starting with ., pseudo-operations do not occupy code segment space
Basic format:
<opcede>{cond}{s}Rd,Rn,#oprand2
<opcede> instruction code
{cond} condition code: 1) plus condition code: the instruction is executed conditionally, 2) without condition code: the instruction is executed unconditionally by default
{s}: add s, affect the CPSR register, do not add s, do not affect the CPSR register
Rd: destination register
Rn: First Operational Register
#oprand2: second operand
1) Immediate number: From the judged number, find the number between 0~0xff===> the judged number contains all 1, and the found number between 0~0xff is shifted to the right by an even number=== > Remove the low bit and make up to the high bit. If you can get the number you want to judge, it means that this number is an immediate number
2) Register
3) Significant number: After inverting a number bit by bit, if the number is an immediate number, it means that the number is a valid number
Precautions:
1. {cond}{s} need to be written together
2. Rd, Rn, #oprand2 need to be separated by commas
3. {cond}{s} and Rd, Rn, #oprand2 need to be separated by spaces
4. An assembly instruction occupies one line, and there is no semicolon, case insensitive
Three, instructions
1. Data operation instructions
1.1 Data movement instruction MOV MVN
equivalent to assignment
Instruction format: {cond}{s} Rd,#oprand2
mov ====> Assign the second operand
mvn ====> After inverting the second operand bit by bit, assign
1.2 Pseudo-instruction LDR
Can be used for assignment of all numbers
Format: ldr register, = value
1.3 Shift operation instruction LSR LSR ROR ASR
Instruction format: {cond}{s} Rd,Rn,#oprand2
lsl: logical left shift =====> Features: unsigned number left shift, high bit out, low bit complement 0
lsr: logical right shift =====> Features: unsigned number right shift, low bit out, high bit complement 0
ror: circular shift to the right =====> Features: the low bit is shifted out, and the high bit is filled
asr: Arithmetic right shift =====> Features: low bit out, high bit complement sign bit
1.4 bit operation instruction AND ORR EOR BIC
Format: {cond}{s} Rd,Rn,#oprand2
and: bitwise AND =====> and 0 to clear 0, and 1 unchanged
orr: bitwise or =====> or 0 is unchanged, or 1 is set to 1
eor: bitwise XOR =====> XOR 0 remains unchanged, XOR 1 is reversed (same as 0, different as 1)
bic: bitwise clear =====> Which bit is written to 1 in the second operation, and the corresponding bit is cleared to 0
1.5 Arithmetic operation instructions ADD ADC SUB SBC MUL
Instruction format: {cond}{s} Rd,Rn,#oprand2
add: common addition instruction
adc: add instruction with carry ====> C bit flag in CPSR register
sub: ordinary subtraction instruction
sbc: subtraction instruction with borrow
mul: multiplication instruction ====> no second operand, {cond}{s} Rd,Rn
1.6 Comparison instruction CMP
Instruction format: {cond} Rn,#oprand2
important point:
1) The comparison instruction has no target register
2) The essence of the comparison instruction is to perform a subtraction operation
3) The execution result of the comparison instruction will affect the NZCV bit of the CPSR register, and there is no need to add s
4) Use comparison instructions and condition codes together
5) All the instructions we learned above are executed unconditionally by default, and the comparison instructions are conditional instructions
2. Jump instruction B BL
Instruction format: b / bl{cond} label ====> Jump to the label, the first instruction is executed
b: There is no return, and the return address of the function will not be saved in the LR register
bl: There is going and returning, and the return address of the function will be saved in the LR register
3. Special function register instruction MRS MSR
Instruction format:
mrs{cond} Rn,cpsr ====> Read the value in the CPSR register into the Rn target register
msr{cond} cpsr,Rn ====> Write the value in the Rn register to the CPSR register
4. Memory operation instructions
1. Single register operation instruction LDR STR
Instruction format:
ldr/ldrb/ldrh Rn,[Rm] ===> Point Rm to the data in the memory space and read it into the Rn target register
str/strb/strh Rn,[Rm] ===> Write the value in the Rn register to the address space pointed to by Rm
ldr ===> looad load ===> read the value in the memory into the register
str ===> store write ===> write the value in the register to a certain memory space
r ===> register ===> 4 bytes
b ===> byte ===> 1 byte
h ===> half word ===> 2 bytes
2. Multi-register operation instruction LDM STM
Command code: ldm stm
Instruction format:
stm{cond} Rm,{register list} ===> Write the data in the register list to the continuous address space pointed to by Rm
ldm{cond} Rm,{target register list} ===> Point Rm to the content in the continuous address space and read it into the target register list
Remarks: 1) The register list is continuously separated by '-' r1-r5
2) The register list is not continuous and separated by ',' to separate r1, r2, r3, r5
5. Stack pointer operation instruction SP
stack pointer register ====> sp
Full stack: The stack pointer points to this space with valid data
Empty stack: the stack pointer points to this space without valid data
Increase the stack: the stack pointer moves to the high address direction
Decrease the stack: the stack pointer moves to the lower address direction
stack type
Full increase stack Full decrease stack Empty increase stack Empty decrease stack
Full stack: stmfa/ldmfa Full Accending
Full desascending stack: stmfd/ldmfd Full Desascending =====> ARM uses full desascending stack by default
Empty accending stack: stmea/ldmea Empty Accending
Empty minus stack: stmed/ldmed Empty Desascending
Commonly used full minus stack
Instruction format (example):
stmfd sp!,{register list} ===> Write the data in the register list to the continuous address space pointed to by the stack pointer
ldmfd sp!,{target register list} ===> Point the stack pointer to the content in the continuous address space and read it into the target register list