Instructions : Mnemonics for CPU machine instructions. For example, the mov instruction will be decoded into machine code (such as: 00011111) by the assembler, and the computer can only recognize the machine code to execute. The instruction is the specific meaning of this string of machine codes that is convenient for us to remember.
Pseudo-instructions : Essentially not instructions, but provided by the compilation environment, they are used to guide the compilation process.
arm has 8 addressing modes :
Register addressing: mov r2, r3 //equivalent to r2 = r3 in c, assign the value of register r3 to r2
Immediate addressing: mov r2, #0 //Assign immediate value 0 to r2
Register shift addressing: mov r2, r3, lsl #2 // shift r3 to the left by 2 bits, and then assign the value to r2
Register indirect addressing: ldr r2, [r3] // Assign the value in the memory address of r3 to r2, which is equivalent to the assignment of pointers in c language
Base address indexing: ldr r2, [ r3, #4] // The value in the address after the memory address in r3 +4 is assigned to r2
Multi-register addressing: ldmia r2!, {r3-r5, r8} //Registers are loaded into memory, that is, r3, r4, r5, r8, and 4 basics are loaded into the memory address stored in r2
Stack addressing: stmfd sp!, {r3-r4, lr} //Similar to multi-register addressing, except that this register can only use the sp register.
Relative addressing: beq flag //Jump to flag if the condition is true, flag is a label, just like goto.
arm common instructions :
- The transfer between the two registers of mov r2 and r3 can also be passed to r2 immediately. The value passed to r2 is unchanged.
- The transfer between the two registers of mvn r2 and r3 can also be passed to r2 immediately. The value passed to r2 is negated.
- Add: add r0, r1, r2 // r0 = r1 + r2
- Subtract: sub r0,r1,r2 //r0 = r1 - r2
- Add instruction with carry: adc{condition}{S} destination register, operand 1, operand 2 . It is used to add the two operands, plus the value of the C condition flag in CPSR, and store the result in the destination register.
- Subtraction instruction with borrow: sbc{condition}{S} Destination register, operand 1, operand 2, subtract operand 1 from operand 2, then subtract the inverse of the C condition flag in CPSR, and set The result is stored in the destination register.
- AND: and r0, r0, #3 ; This instruction keeps bits 0, 1 of r0 and clears the remaining bits. Operand 1 shall be a register, operand 2 may be a register, a shifted register, or an immediate value. This instruction is often used to mask certain bits of operand 1.
- Or: orr r0, r0, #3 ; This instruction sets bits 0 and 1 of r0, leaving the rest of the bits unchanged. Operand 1 shall be a register, operand 2 may be a register, a shifted register, or an immediate value. This instruction is often used to set certain bits of operand 1.
- Logical XOR: eor r0, r0, #3 ; This instruction inverts bits 0, 1 of R0 and leaves the rest of the bits unchanged. Operand 1 shall be a register, operand 2 may be a register, a shifted register, or an immediate value. This instruction is often used to invert certain bits of operand 1.
- Bit clear instruction: bic r0, r0, #%1011 ; This instruction clears bits 0, 1, and 3 in R0, and the rest of the bits remain unchanged. The effect is that bits that are 1 become 0.
- Direct comparison instruction: cmp r1, r0 ; subtract the value of register r1 from the value of register r0, and set the flag bit of CPSR according to the result. The flag bit indicates the relationship between operand 1 and operand 2 (big, small, equal).
- Negative number comparison instruction: cmn r1, r0 ; add the value of register r1 to the value of register r0, and set the flag bit of CPSR according to the result.
- Test instruction tst r1, #0xf ; judge whether bit0 - bit3 of r1 are all 0. Used to test whether the lowest bit is set in register R1 (% means a binary number). The TST instruction is used to perform a bitwise AND operation on the contents of one register and another register or an immediate value, and update the value of the condition flag in the CPSR according to the operation result.
- Bit test instruction: teq r1, r2 ; bitwise XOR the value of the register R1 and the value of the register R2, and set the flag bit of the CPSR according to the result. The TEQ instruction is used to perform a bitwise XOR operation on the contents of one register and another register or an immediate value, and update the value of the condition flag in the CPSR according to the operation result. This instruction is usually used to compare operand 1 and operand 2 for equality.
- Multiplication instruction:
- Program status register access instruction: MRS R0, CPSR ; transfer the content of CPSR to R0
- MSR CPSR, R0 ; transfer the content of R0 to CPSR
- Unconditional jump instruction: b Label ; the program unconditionally jumps to the label Label for execution
- bl Label ; when the program unconditionally jumps to the label Label for execution, save the current PC value to R14 at the same time
- Access memory instruction: ldr r0, [r1] ; read the word data whose memory address is R1 into register R0. (The RISC architecture adopted by arm, the cpu cannot directly read the memory, but it has to be loaded into the general-purpose register of the cpu for processing, and then returned to the memory. That is to say, to change the value in the memory, you must first read the value in the memory to the CPU's In the register, the value is changed through the register, and then the value in the register is stored in the memory.)
- str r0, [r1], #8 ; write the word data in R0 into the memory with R1 as the address, and write the new address R1+8 into R1.
- swp r0, r1, [r2] ; Read the value of the memory address of r2 into the register r0, and then write the value of r1 into the memory address of r2 to complete the data exchange.
Directives :
- .global _stat: .global is the external link attribute for start
- .section .text : Specify the current segment code segment
- .ascii .byte .short .long .word Define variable
- .quad .float .string Define data
- .align 4 Align with 16 bytes
- .balignl 16 0xabcdefgh 16-byte alignment, 4-byte padding
- .equ is similar to the macro definition of C language, and can also be defined directly using #define. Assembly and C language are interlinked.
- .end end of file
- .include is used to include header files
- .arm / .code32 declarations are arm instructions
- The .thumb .code16 declaration is the thumb instruction
- ldr: The immediate value is not legal. Generally, the immediate value with more than 8 digits is not 0 is considered illegal. However, if the instruction ldr uses an illegal immediate value, an error will be reported. So arm invented the ldr pseudo-instruction, and it is okay to use illegal immediate numbers. Generally, we use the ldr of the pseudo-instruction.
Instruction plus suffix : such as: ldr
- ldrb, add b, the function remains the same, but the length of the operation becomes 8 bits
- ldrh, add h, the function remains the same, but the length of the operation becomes 16 bits
- ldrs, add s, the function remains the same, but becomes signed
- Another one is to add s, which is to change the flag bit of cpsr, which is different from the above, such as movs, after adding s, it will change the flag bit of cpsr.
Conditions add suffixes : such as moveq r2, r3. See if the flag bit z of the execution result of the previous sentence is equal to 1, if it is equal to execute this instruction, if not, skip this instruction and execute the next sentence of this sentence. These conditional suffixes are as follows:
