Generally, when we have a lot of project files, it is more troublesome to use the gcc tool to directly type the compile command, so the advantage of writing makefile comes. You only need to type make to compile each time.
Here is a universal version, no matter how many files in the current directory, you only need to make, without modifying the makefile, directly generate the main executable program
The following is the makefile
#Cross compilation tool chain #CC=arm-linux-gnueabihf-gcc
CC=gcc
# Link library
CFLAGS = -lm -lpthread
#Get c file SrcFiles=$(wildcard *.c)
#Use the replacement function to obtain .o files OBJS = $ (patsubst %.c,%.o,$(SrcFiles))
all:main
main:$(OBJS)
$(CC) -o $@ $^ $(CFLAGS)
%.o:%.c
$(CC) -c $< $(CFLAGS)
.PHONY:clean all
clean:
rm -rf $(OBJS)
rm -rf main
Supplement here
The wildcard function is to obtain the specified file
patsubst function, which has a replacement function.
$(Files), take the value of the File variable.
$@ target file
$^ all dependent
$< first dependent
$? first dependent change