GNU make command, makefile writing

Introduction to makefile

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• The makefile can realize the automatic compilation of the project, and only one make command can be completed with one click. The makefile defines some rules that specify which files need to be compiled first, then compiled, and recompiled.

• General C or C ++ programs need to be compiled into an intermediate file first. The .obj file under Windows and the .o file under UNIX are called compile.

• Each original file should correspond to an intermediate file (.obj file or .o file). The process of synthesizing a large number of intermediate files into an execution file is called link. When linking, the main function and variable are linked Use .obj files or .o files to link applications. The linker only concerns the intermediate files of the function, and does not care about the location of the source files. In order to avoid the complicated management of a large number of intermediate files, the intermediate files need to be packaged. It is called a library file (library file) under Windows, ie. Archive File, that is. A file.

makefile rules

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Process

目标 : 需要的条件(注意 : 两边的空格)
    命令(以Tab键开头)

explain:

• 目标 Can be one or more, can be ObjectFile file, execution file, or even label
• 条件 Refers to the dependent file or target
• 命令 Refers to the script that needs to be executed to generate the target

Summary: That is, a makefile rule defines the dependencies of the compilation, the target file depends on the conditions, and the command to generate the rules

for example

objects = main.o kbd.o command.o display.o /
              insert.o search.o files.o utils.o
    edit : $(objects)
            cc -o edit $(objects)
    main.o : main.c defs.h
            cc -c main.c
    kbd.o : kbd.c defs.h command.h
            cc -c kbd.c
    command.o : command.c defs.h command.h
            cc -c command.c
    display.o : display.c defs.h buffer.h
            cc -c display.c
    insert.o : insert.c defs.h buffer.h
            cc -c insert.c
    search.o : search.c defs.h buffer.h
            cc -c search.c
    files.o : files.c defs.h buffer.h command.h
            cc -c files.c
    utils.o : utils.c defs.h
            cc -c utils.c
    clean :
            rm edit $(objects)

make command

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1. First find the "makefile" or "Makefile" file in the current directory, then locate the first target file (target), in the above example, you will find the "edit" file, and use this file as the final target file
2. If the eidt file does not exist, or the modification time of the .o file that is dependent after eidt is newer than the edit file, execute the command defined later to generate the edit file
3. If the .o file that depends on edit does not exist, make will look for the dependency of the .o file in the current file. If it is found, the .o file is generated according to that rule. The c and .h files exist, and make generates the .o file , And finally execute edit

Automatic derivation

The GNU make command supports automatic derivation. As long as make sees a .o file, it will automatically add the .c file to the dependency relationship. The above example can be simplified to the following form

objects = main.o kbd.o command.o display.o /
              insert.o search.o files.o utils.o
    edit : $(objects)
            cc -o edit $(objects)

    main.o : defs.h
    kbd.o : defs.h command.h
    command.o : defs.h command.h
    display.o : defs.h buffer.h
    insert.o : defs.h buffer.h
    search.o : defs.h buffer.h
    files.o : defs.h buffer.h command.h
    utils.o : defs.h
　　clean :
            rm edit $(objects)

File function

make supports multi-file co-simplification rules, the above example can be further simplified to the following form (but not recommended because it is more difficult to maintain)

objects = main.o kbd.o command.o display.o /
              insert.o search.o files.o utils.o
    edit : $(objects)
            cc -o edit $(objects)

    $(objects) : defs.h
    kbd.o command.o files.o : command.h
    display.o insert.o search.o files.o : buffer.h
    clean :
            rm edit $(objects)

Clear target file rules

Each makefile should clearly write a clearing target (.o and execution file) rule, which is conducive to recompilation and clearing of files.

.PHONYIndicates that clean is a "pseudo target", and the minus sign before rm indicates that some files have problems but don't worry, continue to go down.

Clean is placed at the end of the file by default, otherwise it will be used as the default target.

 `一般的风格为：`
clean:
            rm edit $(objects)
`较为稳健的方法：`
.PHONY : clean
        clean :
                -rm edit $(objects)

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make compile and install

Process

• First download .tar.gzor .tar.bz2package file

• tarUnzip using command

• Enter the file directory after decompression (because make is to search the current file location)

• Use ./configure -prefix={Your Install Path}(other configure parameters Baidu)

• Make compilation (or use make all, the process is sometimes slow, sometimes it will report an error, it may be a problem of dependent packages, you can solve the dependency relationship)

• make install Installation (requires sufficient permissions, some software requires make check or make test for testing)

• make clean Clear intermediate files (Objectfile or .o files) generated by compilation

for example

//1.解压缩
tar -zxf xxxxx-4.0.2.tar.gz  
//2.进入目录
cd xxxxx-4.0.2
//3.配置
./configure --prefix=/usr/local/xxxxx     
//4.编译
make all
//5.安装
make install && make install-init && make install-commandmode && make install-config
//6.清除中间文件
make clean

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Related Links

• http://blog.csdn.net/haoel/article/details/2887
• http://www.cnblogs.com/xwdreamer/p/3623454.html
• http://www.linuxidc.com/Linux/2011-02/32211.htm