Composition principle --- CPU structure and function

CPU structure

CPU function

• For von Neumann-structured computers, once the program enters the memory, the computer can automatically complete the tasks of fetching instructions and executing instructions. The controller is responsible for coordinating and controlling each computer component to execute the instruction sequence of the program.
• Instruction fetch : The controller is required to automatically form the address of the instruction, issue an instruction fetch instruction, and fetch the instruction corresponding to this address into the controller. The address of the first instruction can be specified manually or set by the system.
• Analysis instruction : analyze what operation to be completed, that is, what operation command the controller needs to issue. Analyze the address of the operand participating in this operation, that is, the effective address of the operand.
• Execution instruction : Form the operation control signal sequence, and execute each instruction through the operation of the memory, the arithmetic unit and the IO device.
• Control the input of the program and the output of the operation result and the management of the bus, deal with the abnormal conditions and special requests that occur during the operation of the processor, that is, the interruption processing ability.

CPU block diagram

CPU registers

• User-visible registers: registers where the CPU performs machine language access. Before calling the subroutine, the contents of all user-visible registers must be saved, either automatically by the CPU or programmed by the programmer.

  General register: It can be used to store operands, and can also be used as a register to meet a certain addressing mode.

  Data register: store the operand.

  Address register: store the address.

  Condition code register: stores the condition code, which is partially transparent to the user.

• Control and status registers: transparent to users

  MAR: memory address register.

  MDR: memory data register.

  PC: program counter.

  IR: instruction register.

control unit

• Provides micro-operation command sequence components that complete all computer instruction operations

Instruction cycle

• Instruction cycle: The total time required by the CPU to fetch and execute an instruction is called the instruction cycle, which is the time it takes the CPU to complete an instruction. Completing the operation of executing instructions is also called the execution cycle. Due to the different operating functions, the instruction cycles of various instructions are different.
• Instruction fetch cycle fetch instruction fetch, inter-address cycle fetch effective address fetch, execute cycle fetch operand fetch, interrupt cycle protection program breakpoint.

Instruction cycle data flow

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  The address of the current instruction is stored in the data stream PC of the fetch cycle . This address is sent to the MAR and sent to the address bus, and then the control unit CU sends a read command to the memory, so that the content of the unit pointed to by the corresponding MAR is sent to the MDR via the data bus , And then sent to IR, and the CU controls the PC to add 1, forming the address of the next instruction.
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  Once the data stream of the inter-address cycle is over, the CU checks the content in the IR and determines whether it has inter-address operation. If the inter-address operation is required, the right N bits of the formal address in the MDR will be sent to the MAR , And then sent to the address bus, after which the CU sends a read command to the memory to obtain a valid address and save it to the MDR.
• Execution cycle data flow
  Because different instructions have different operations in the execution cycle, the execution cycle data flow is diverse, which may involve data transfer between CPU internal registers, read and write operations to memory or IO, or ALU Operation cannot be represented by a unified data flow.
• The data flow of the interruption cycle The
  
  content of the current PC must be saved so that the interruption service routine can be accurately returned to the interruption of the program after the execution of the interruption service routine. The CU sends the special geological memory for storing program breakpoints to the MAR and sends it to the address bus. Then the CU sends a write command to the memory and sends the contents of the PC to the MDR. Finally, the program breakpoint passes through the data bus Stored in the memory, in addition, the CU also needs to send the entry address of the program to the PC to prepare for the fetch cycle of the next instruction cycle.