Systemverilog (Green Book) Chapter 2-Data Types

In Verilog, beginners often can't tell the difference between reg and wire, which of them should be used to drive the port? What should I do when connecting different modules? This has been improved in Systemverilog, as shown in Figure 1:

FIG, yellow logic, bit, logic and reg  is an unsigned type ; blue integer, byte, shortint, int and longint is a signed type . For the assignment of four-valued logic and two-valued logic, the following question 1:

logic    [7:0]    a = 8'b1000_0000;
bit      [7:0]    b = 8'b1000_0000;
byte              c = 8'b1000_0000;
initial    begin
    $display("a = %d", a);
    $display("b = %d", b);
    $display("c = %d", c);
end

The printed values ​​are: 128, 128, -128;

Answer: logic and bit; these two are unsigned numbers, so a = b = 128. Byte is a signed value, and the first bit of the value is the sign bit. Therefore, when calculating the value of c = 8'b1000_0000, first subtract 1 = 8'b0111_1111 from the value of c, and then reverse the values ​​of c. 128, at this time c value is -128.

 

When the bit widths of two values ​​are different, how is the operation performed between the values? As in question 2:

byte    signed_vec = 8'b1000_0000;
bit     [8:0] result_vec;
     
initial begin
         result_vec = signed_vec;
         $display("@1 result_vec = 'h%x", result_vec);
         result_vec = unsigned'(signed_vec);
         $dispaly("@2 result_vec = 'h%x", result_vec);
end
   

Signed signed_vec itself is 8 bits. If it is required to assign an unsigned 9-bit value result_vec at this time, it is extended by one bit signed_vec = 9'b11000_0000 = 9'h180.

Use the conversion symbol ' to convert the 8-bit unsigned value, and then assign it to a 9-bit unsigned value, the first bit is filled with 0, then the output is 9'h080.

For data format conversion, as shown in Figure 2: 

Because the four-valued logic includes the x and z types that the two-valued logic does not have, what kind of things will happen when assigning the four-valued logic to the two-valued logic when performing numerical conversion? As shown in question 3:

logic    [3:0] x_vec = 'b111x;
bit      [2:0] b_vec;

/implicit conversion
initial begin
    $display("@1 x_vec = 'b%b", x_vec)；
    b_vec = x_vec;
    $display("@2 b_vec = 'b%b", b_vec);
end

Here, when unsigned four-valued logic is assigned to unsigned two-valued logic, since the four-valued logic is 4 bits and the two-valued logic is three bits, the high bits of the four-valued logic will be truncated. And the four-valued logic x reaches the two-valued logic is 0 .