content:
- precise and imprecise exception
- exception order
- naming dependence
- multicycle operations
- branch delay slot
1. when an instruction is guaranteed to complete, it is called committed. In MIPS integer pipeline, all instructions are committed when they reach the end of the MEM stage and no instruction updates the state before that stage.
if the pipeline can be stopped so that the instructions just before the faulting instruction are completed and those after it can be restarted from scratch, the pipeline is said to have precise exceptions.
although we know which instruction caused the exception, without additional hardware support the exception will be imprecise because the instruction will be half-finished, restarting the instruction stream after such an imprecise exception is difficult.
2. each instruction has its own register to record the state of exception, and each type of exception has its corresponding flag. when the exception occurs, the flag is set which will block the request of the next exception. so the handler of exception will be executed with the sequence of exceptions rather than the sequence of instructions.
3. although two instructions that don't have any data stream flowing but the breaking of naming dependence could cause chaos in processes of saving data in registers. the solution of this dependence is changing one of the registers which are used in the project.
4. different execution has a different hardware component to handle. so the execution stage can be divided into several parts. some parts are pipelined which means that the next execution doesn't need to wait for the previous instruction get out of the EX stage. on the contrary, for unpipelined executions like integer division part, next operation should wait until the finishing of previous one.
different parts in EX stage can work contemporarily.
5. branch delay slot: it appears behind the branch judgment instruction. which is because of the additional IF stage at the beginning of the branch entity. (based on the optimized structure)
