Content:
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Control hazard
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UML language
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Control hazard
Control hazard happens when we have branch instruction in the program. The reason is that the computer doesn’t know the address of next instruction before the branch instruction reaches the MEM stage, which will cause 3 clock cycles as penalty. (Instruction fetch stage needs the result of branch judgements)
to reduce the amount of penalty, we move the address adder and judgment component to the ID stage. In this way, we could get the address of next instruction at the end of ID stage, so that we could reduce penalty to 1 clock cycle. The consequence of this change on hardware is that in the next instruction, we have to take instruction fetching stage 2 times.
- UML language is a kind of language used to modeling the process of building a project.
We have to draw this diagram before we start coding
