Verilog Syntax

Notes when I learned Verilog

Basic

-6'd3;	// negative number

x	// x unknown or don't care, z or? high impedence(unconnected)
-6'd3_3;	// _ allowed anywhere in number －》 readable

wire a;	// 1 bit default
reg signed [63:0] a;	// reg retain value until another value is placed
reg	[0:40] vm;	// vm[0] is most significant bit

a[31-:8];	// a[31:24]
vm[24+:8];	// vm[24, 31] 
reg [4:0] port_id[0:7];	//8 elements 5 bits array
parameter port_id = 5;	// constant

'define WORD_SIZE 32;	
// used as 'WORD_SIZE

Assignment

// Continuous assign. out must be net/ concatenated net
assign out = i1&i2;
assign {cout, sum[3:0]} = a[3:0] + b[3:0] + cin;

wire #10 out = in1 & in2;
assign #10 out = in1 & in2; // Delay in a continous assign. Do computation after 10.

// Replication concatenate
Y = {4{A}};

// Procedural assign (blocking / non-blocking)
// blocking
initial
begin
	#1 x = 0;
	#15 y = 1;	// executed at time 16
end

// non-blocking
initial
begin
	x <= #1 0;
	#15 y = x;	// executed at time 15
end

always @(posedge clock)
// @posedge the value to the right hand side is read and stored, after delay(or no delay), the stored value is written to reg
begin
	reg1 <= #1 in1;	
	reg2 <= @(negedge clock) in2 ^ in3;
	reg3 <= #1 reg1;
end

// Intra-assignment delay control
initial
begin
	x = 0;
	z = 0;
	#0 w = 5;	// 该时刻最后执行 zero-delay
	y = #5 x + z;	// 立马执行，然后过5s再assign
end

// event
event received_data;

always @(posedge clock)
begin
	if (condition)
		->received_data;	// trigger
end

always @(received_data)
	...

if (condition)
// statement must be grouped if multiple statements exist.
begin
...
end
else
begin
...
end