ram verilog

/*
** This example shows the use of the Vivado ram_style attribute
**
** Acceptable values are:
** block : Instructs the tool to infer RAMB type components.
** distributed : Instructs the tool to infer LUT RAMs.
**
******************************************************************/


module ram_inf_64x1d_2 (a, dpra, clk, din, we, spo, dpo);


parameter ADDRESSWIDTH = 6;
parameter BITWIDTH = 1;
parameter DEPTH = 34;

input clk, din, we;
input [ADDRESSWIDTH-1:0] a, dpra;

output spo, dpo;

(* ram_style = "block" *)
reg [BITWIDTH-1:0] ram [DEPTH-1:0];
reg [ADDRESSWIDTH-1:0] read_dpra; 
reg [ADDRESSWIDTH-1:0] read_a; 


always @(posedge clk) begin
if (we) begin
ram [a] <= din;
end
read_a <= a;
read_dpra <= dpra;
end

assign spo = ram [read_a];
assign dpo = ram [read_dpra];


endmodule