Verilog Operators

以virtex-5为例。

Operators（操作符）分为 Arithmetic、Bitwise、Logical、Replicate/Concatenate、Shift、Unary Reduction。

1、Arithmetic

// The following are the arithmetic operators as defined by the Verilog language.
// 
//    + .... Addition
//    - .... Subtraction
//    * .... Multiplication
//    / .... Divide
//    % .... Modulus
//    ** ... Power Operator (i.e. 2**8 returns 256)

*：综合工具会将其综合为COMBMULTIPLIER或COMBMULTIPLIERCONSTANT(如果两个操作数中有一个为常数)。具体实现会用LUT或DSP48E。可使用DSP48E原语。例：a * b = (a[1] * 2 + a[0]) * (b[1] * 2 + b[0])。

/、%：第一个操作数不是常数时，/ 和%的第二个操作数只能为常数且是2的幂，不然综合时会报错。如果不是常数，会报错：Can not simplify operator DIV(MOD).如果不是2的幂，会报错：Operator /(%) is only supported when the second operand is a power of 2.如果是常数且是2的幂，即相当于取第一个操作数的前几位（/）或后几位（%）。第一个操作数为常数时，第二个操作数必须为常数。

**：Operator ** is only supported when both operands are constant.即只支持常数的操作（使代码方便阅读）。

2、Bitwise

// The following operators can be used on two single bits to produce a single bit 
// output or two equivalent sized bused signals where the operations are performed 
// on each bit of the bus. In the case of the Invert, only one signal or bus is 
// provided and the operation occurs on each bit of the signal.
// 
//    ~ .... Invert a single-bit signal or each bit in a bus
//    & .... AND two single bits or each bit between two buses
//    | .... OR two single bits or each bit between two buses
//    ^ .... XOR two single bits or each bit between two buses
//    ~^ ... XNOR two single bits or each bit between two buses

3、Logical

// The following logical operators are used in conditional TRUE/FALSE statements 
// such as an if statement in order to specify the condition for the operation.
// 
//    ! .... Not True
//    && ... Both Inputs True
//    || ... Either Input True
//    == ... Inputs Equal
//    === .. Inputs Equal including X and Z (simulation only)
//    != ... Inputs Not Equal
//    !== .. Inputs Not Equal including X and Z (simulation only)
//    < .... Less-than
//    <= ... Less-than or Equal
//    > .... Greater-than
//    >= ... Greater-than or Equal

4、Replicate/Concatenate

// The following operators either concatenates several bits into a bus or replicate 
// a bit or combination of bits multiple times.
// 
//    {a, b, c} .... Concatenate a, b and c into a bus
//    {3{a}} ....... Replicate a, 3 times
//    {{5{a}}, b} .. Replicate a, 5 times and concatenate to b

5、Shift

// The following operators will shift a bus right or left a number of bits.  
// 
//    << .... Left shift (i.e. a << 2 shifts a two bits to the left)
//    <<< ... Left shift and maintain sign bit
//    >> .... Right shift (i.e. b << 1 shifts b one bits to the right)
//    >>> ... Right shift and maintain sign bit

本来以为算术右移">>>"一定会保留符号位的，但之前用modelsim仿真时遇到一个很奇怪的问题。算术右移有时会保留符号位，但有时却补零，具体何时会出现哪种情况没仔细研究过。解决办法：当用到算术右移时，将操作数定义为有符号数。对于使用其他操作符运算时，同样如此。

6、Unary Reduction

// The following operators can be used on a bussed signal where all bits in the bus 
// are used to perform the operation and a single bit output is resolved.
// 
//    & .... AND all bits together to make single bit output
//    ~& ... NAND all bits together to make single bit output
//    | .... OR all bits together to make single bit output
//    ~| ... NOR all bits together to make single bit output
//    ^ .... XOR all bits together to make single bit output
//    ~^ ... XNOR all bits together to make single bit output